一种基于TSV和激光刻蚀辅助互连的改进型CIS封装

发布时间：2018-04-18 09:29

本文选题：硅通孔(TSV) + 低温电感耦合等离子体增强型化学气相淀积(ICPECVD)　；参考：《半导体技术》2017年08期

【摘要】：提出了一种基于硅通孔(TSV)和激光刻蚀辅助互连的改进型CMOS图像传感器(CIS)圆片级封装方法。对CIS芯片电极背部引出的关键工艺,如锥形TSV形成、TSV绝缘隔离、重布线(RDL)等进行了研究。采用低温电感耦合等离子体增强型化学气相淀积(ICPECVD)的方法实现TSV内绝缘隔离;采用激光刻蚀开口和RDL方法实现CIS电极的背部引出;通过采用铝电极电镀镍层的方法解决了激光刻蚀工艺中聚合物溢出影响互连的问题,提高了互连可靠性。对锥形TSV刻蚀参数进行了优化。最终在4英寸(1英寸=2.54 cm)硅/玻璃键合圆片上实现了含有276个电极的CIS圆片级封装。电性能测试结果表明,CIS圆片级封装具有良好的互连导电性,两个相邻电极间平均电阻值约为7.6Ω。
[Abstract]:A wafer level packaging method for an improved CMOS image sensor based on silicon through hole (TSVV) and laser etching assisted interconnection is proposed in this paper.The key technology of back extraction of CIS chip electrode, such as tapered TSV to form insulation isolation, rewiring, etc., has been studied in this paper.The low temperature inductively coupled plasma enhanced chemical vapor deposition (ICP-ECVD) method is used to isolate the internal insulation of TSV, the laser etching opening and the RDL method are used to realize the back extraction of the CIS electrode.By means of electroplating nickel layer with aluminum electrode, the problem of polymer spillover affecting interconnection in laser etching process is solved, and the interconnect reliability is improved.The etching parameters of conical TSV were optimized.Finally, CIS wafer packaging with 276 electrodes was realized on 4 inch / 1 inch / 2.54 cm) silicon / glass bonded wafer.The electrical performance test results show that the CIS wafer packaging has good interconnection conductivity, and the average resistance between the two adjacent electrodes is about 7.6 惟.
【作者单位】：上海大学索朗光伏材料与器件R&D联合实验室;中国科学院上海微系统与信息技术研究所传感技术联合国家重点实验室;
【基金】：国家自然科学基金资助项目(61574154) 上海市自然科学基金资助项目(13ZR1447300)
【分类号】：TN405;TP212

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