低电压低功耗模数转换器的研究与设计

发布时间：2018-04-19 09:58

本文选题：低功耗 + SAR　；参考：《杭州电子科技大学》2015年硕士论文

【摘要】：低功耗模数转换器(ADC)广泛应用于各种采用电池供电的便携式电子产品中,如移动电话、平板电脑、智能穿戴设备和各种便携式医疗设备等。为了延长设备的使用周期,就必须降低芯片的功耗;同时为了满足多路信号的采集需求,就要求ADC具有多个输入通道。低功耗ADC的设计难点在于希望在降低ADC功耗的同时,不会过多损失ADC的性能和增加ADC的实现成本。为了实现一款低功耗多通道高性能的ADC,本文开展相关的研究工作,完成的主要成果如下:(1)采用了低成本低功耗的ADC实现架构。通过对比不同的ADC实现架构的优缺点,本文选择了适用于低功耗低成本的逐次逼近型模数转换器(SAR ADC)结构;同时采用了低电压的设计方案。该芯片采用CMOS 0.35μm工艺实现,标准电压为3.3V。为了降低ADC的整体功耗,芯片最低工作电压可从3.3V降低到1.8V,从而减少了约45%的功耗。由于MOSFET的阈值没有降低,所以在设计MOS开关、比较器、偏置电路等时,低电压设计方案具有一定的难度。(2)在芯片实现过程中,设计了低功耗低成本的分段式电荷共享型DAC结构。电荷共享型DAC使用电容阵列实现,没有静态功耗,具有较高的匹配精度,适合低功耗的应用场合。本文采用分段式电荷共享型DAC结构可以进一步减小整体电容阵列的面积,从而达到低成本低功耗的要求。(3)为了满足低电压低功耗高性能的要求,设计了具有轨到轨输入级的再生锁存型比较器。轨到轨输入级采用1:1电流镜偏置复用技术,通过亚阈值设计,在实现低功耗的同时减小了比较器的失调电压。再生锁存级设计了迟滞特性,可以有效消除由于回踢噪声造成的比较器的误翻转,从而提高了比较器的抗干扰能力。测试结果表明该ADC芯片是一个可用低至1.9V供电的4通道、10位分辨率、300ksps采样率的低电压低功耗逐次逼近型模数转换器(SAR ADC),芯片核心版图面积为1.23mm2,并采用Chartered CMOS 0.35μm工艺进行了流片实现。测试结果表明在2V供电,166ksps的采样速率下,ADC的功耗只有200μW;计算得到的ADC的信噪比(SNR)为58.25dB,无杂散动态范围(SFDR)为60dB,INL和DNL小于0.2LSB,有效位数约为9.4bit,品质因子(FOM)为4.9pJ/conversion-step。
[Abstract]:Low power A / D converter (ADC) is widely used in a variety of battery-powered portable electronic products, such as mobile phones, tablets, smart wearables and various portable medical devices.In order to prolong the service life of the device, the power consumption of the chip must be reduced, and in order to meet the demand of multi-channel signal acquisition, the ADC is required to have multiple input channels.The design difficulty of low power ADC is to reduce the power consumption of ADC without losing the performance of ADC and increasing the cost of ADC implementation.In order to achieve a low power multi-channel high performance ADCs, this paper carries out related research work. The main results are as follows: 1) A low cost and low power ADC implementation architecture is adopted.By comparing the advantages and disadvantages of different ADC implementation architectures, this paper chooses the successive approximation ADC structure which is suitable for low power and low cost, and adopts a low voltage design scheme.The chip is realized by CMOS 0.35 渭 m process and the standard voltage is 3.3 V.In order to reduce the overall power consumption of ADC, the minimum operating voltage of the chip can be reduced from 3.3 V to 1.8 V, thus reducing the power consumption by about 45%.Because the threshold of MOSFET is not reduced, when designing MOS switch, comparator and bias circuit, it is difficult to design low voltage design scheme. In the process of chip implementation, a low power and low cost segmented charge-sharing DAC structure is designed.The charge-sharing DAC is realized by capacitive array with no static power consumption and high matching precision. It is suitable for low power consumption applications.In order to meet the requirements of low voltage, low power consumption and high performance, the area of the whole capacitor array can be further reduced by using a segmented charge sharing DAC structure, which can meet the requirements of low cost and low power consumption.A regenerative latch comparator with rail-to-rail input stage is designed.The 1:1 current mirror bias multiplexing technique is used in the rail to rail input stage. By the design of sub-threshold, the offset voltage of the comparator is reduced while the power consumption is low.The hysteresis characteristic of regenerative latch stage is designed, which can effectively eliminate the false overturn of comparator caused by backkick noise and improve the anti-jamming ability of comparator.The test results show that the ADC chip is a low voltage and low power successive approximation ADC with low voltage and low power consumption. The core area of the chip is 1.23mm ~ 2, and the Chartered CMOS 0.35 渭 m process is adopted. The chip is a low voltage and low power successive approximation type A / D converter with low power sampling rate of 300ksps and 4-channel power supply of up to 1.9 V.The flow sheet is realized.The test results show that the power consumption of the ADC is only 200 渭 W at the sampling rate of 166ksps, the SNR of the calculated ADC is 58.25dB, the non-spurious dynamic range of SFDR is 60dBINL and DNL is less than 0.2LSB. the effective digit is about 9.4 bit and the quality factor is 4.9pJConversion-step.
【学位授予单位】：杭州电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN792

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