基于高层次综合的AES算法研究与设计

发布时间：2018-04-22 12:31

本文选题：对称密钥加密算法 + 高级加密标准　；参考：《计算机应用》2017年05期

【摘要】：由于对广泛使用的AES算法的性能要求越来越高,基于软件的密码算法已经越来越难以满足高吞吐量密码破解的需求,因此越来越多的算法利用现场可编程逻辑门阵列(FPGA)平台进行加速。针对AES算法在FPGA硬件上存在的开发复杂度高且开发周期长等问题,采用高层次综合(HLS)设计方法,使用高级程序语言描述并设计AES硬件加速算法。首先利用循环展开等提高运算并行度;其次使用资源平衡技术进行优化,充分利用片上存储和电路资源;最后添加全流水结构,提高整体设计的时钟频率和吞吐量,同时也详细对比分析基准设计、利用结构展开、资源均衡以及流水线优化方法的设计。经过实验表明,在Xilinx xc7z020clg484 FPGA芯片上,最终AES算法的时钟频率最高达到127.06 MHz,而吞吐量达到了16.26 Gb/s,较之基准的AES设计,性能提升了三个数量级。
[Abstract]:Due to the increasingly high performance requirements of widely used AES algorithms, software-based cryptography algorithms have become more and more difficult to meet the needs of high-throughput cryptographic cracking. Therefore, more and more algorithms are accelerated by FPGA platform. Aiming at the problems of high complexity and long development cycle of AES algorithm on FPGA hardware, the method of high-level synthesis is used to design and describe and design the accelerated algorithm of AES hardware using high-level programming language. At first, the parallel degree of operation is improved by using loop expansion and so on; secondly, the technology of resource balance is used to optimize and make full use of on-chip storage and circuit resources; finally, the whole pipeline structure is added to improve the clock frequency and throughput of the whole design. At the same time, the design of benchmark design, structure expansion, resource balance and pipeline optimization are compared in detail. The experiments show that the clock frequency of the final AES algorithm is up to 127.06 MHz on Xilinx xc7z020clg484 FPGA chip, and the throughput is 16.26 GB / s, which is three orders of magnitude higher than the standard AES design.
【作者单位】：中国科学院信息工程研究所;信息内容安全技术国家工程实验室;北京特种工程设计研究院;
【基金】：国家自然科学基金青年科学基金资助项目(61402475) 新疆自治区科技专项(201230123)~~
【分类号】：TN791;TP309.7

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