低功耗混合逻辑电路设计

发布时间：2018-04-23 13:42

本文选题：漏电流 + 漏功耗　；参考：《宁波大学》2015年硕士论文

【摘要】：随着集成电路的发展,集成电路的规模越来越大,集成度越来越高,大规模集成电路的性能决定着电子设备的性能。目前,移动终端电子设备对于集成电路芯片的性能要求越来越严格,伴随着工艺制程的进步,漏电流的种类越来越多,漏功耗占电路总功耗的比重越来越大,因此高速低功耗集成电路芯片的设计已经成为集成电路行业发展的必然趋势。加法运算是在数字电子系统中最基本的算术逻辑运算,加法器是数字系统中最基本的逻辑运算单元,它常常应用于多位加法器的进位关键路径中,是影响电子设备性能的重要因素之一。本文列举了多种常用加法器,通过对串行进位加法器、线性进位选择加法器、超前进位加法器、曼彻斯特加法器等的研究,分析了其基本原理以及进位关键路径的逻辑翻转。本学位论文通过对传统的低功耗CMOS集成电路加法器进行认真研究,总结了传统加法器的优缺点,在此基础上,通过优化算法和改进电路拓扑结构,分别设计了新型4位超前进位加法器和新型4位栅压自举加法器。对电路图在SMIC130nm工艺、四种不同输入频率、不同负载条件下用HSPICE进行电路仿真,以速度、功耗、功耗延时积为性能指标,分别对电路进行综合对比和分析。仿真结果表明新型超前进位加法器的功耗延时积相比于串行进位加法器和传统超前进位加法器分别减小了70%-72%和64%-66%;新型栅压自举加法器的功耗延时积相比于其他类型的4位加法器减小了5%-45%。通过实验数据,进一步证明了新型超前进位加法器和新型栅压自举加法器的优良性能,为集成电路设计者提供了一个可靠的选择。
[Abstract]:With the development of integrated circuits, the scale of integrated circuits becomes larger and larger and the level of integration becomes higher and higher. The performance of large-scale integrated circuits determines the performance of electronic devices. At present, the performance requirements of mobile terminal electronic devices for IC chips are more and more stringent. With the progress of the process, there are more and more kinds of leakage current, and the proportion of leakage power to the total power consumption of the circuit is increasing. Therefore, the design of high-speed and low-power IC chips has become an inevitable trend in the development of integrated circuit industry. Addition is the most basic arithmetic and logic operation in the digital electronic system. The adder is the most basic logic operation unit in the digital system. It is often used in the carry-critical path of the multi-bit adder. It is one of the important factors that affect the performance of electronic equipment. This paper enumerates many kinds of commonly used adder, through the research of serial carry adder, linear carry selection adder, lead carry adder, Manchester adder and so on, analyzes its basic principle and the logical flip of the carry-critical path. In this dissertation, the advantages and disadvantages of the traditional low power CMOS integrated circuit adder are summarized. On the basis of this, the circuit topology is optimized and the circuit topology is improved. A new 4-bit carry adder and a new 4-bit gate voltage bootstrap adder are designed respectively. The circuit is simulated by HSPICE in SMIC130nm process with four different input frequencies and different loads. The circuit is compared and analyzed with the performance index of speed, power consumption and power delay product. The simulation results show that compared with serial carry adder and traditional carry adder, the power delay product of the novel advanced carry-adder is reduced by 70-72% and 64-66, respectively, and the power delay product of the new type of gate voltage bootstrap adder is lower than that of other categories. The 4-bit adder reduces the number by 5-45. Through the experimental data, the excellent performance of the new advanced carry adder and the new gate voltage bootstrap adder is further proved, which provides a reliable choice for the IC designers.
【学位授予单位】：宁波大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN791

【参考文献】