纳米工艺下低漏功耗CMOS标准单元的设计

发布时间：2018-04-23 22:05

本文选题：漏功耗 + 标准单元包　；参考：《宁波大学》2015年硕士论文

【摘要】：随着集成电路的迅速发展,CMOS超大规模集成电路(VLSI)设计工艺已进入纳米尺度,纳米MOS器件阈值电压的缩小使得芯片的漏电流呈指数形式增加,从而造成芯片漏功耗的迅速增大,漏功耗已成为芯片总功耗中不可忽略的组成部分。标准单元在数字ASIC集成电路设计中的作用非常重要,减小标准单元的功耗将会使ASIC芯片的总功耗降低。在纳米工艺下,降低标准单元的漏功耗将直接影响ASIC芯片漏功耗水平。因此研究低漏功耗标准单元对低漏功耗ASIC芯片的设计有着非常重要的意义。本文介绍了CMOS电路的漏功耗降低技术和标准单元建库技术的相关知识背景。在NCSU 45nm工艺下,开展标准单元低漏功耗技术的研究,构建了一个低漏功耗标准单元包,为基于标准单元的低漏功耗ASIC设计提供了基础。本课题的研究分为以下几个部分:1、研究纳米工艺下漏功耗减小技术,并应用于标准单元设计中。采用沟长调制技术对NCSU 45nm工艺的标准单元进行分析,并对标准单元的晶体管尺寸进行优化,以期达到减小漏功耗的目的;根据优化的晶体管尺寸进行了常用标准单元的低漏功耗设计,主要包括常用组合逻辑门电路和触发器等标准单元;基于功控休眠技术提出了一种新的具有数据保持功能的低漏功耗主从D触发器结构;2、对低漏功耗标准单元进行版图库的设计。绘制低漏功耗标准单元的版图,然后采用Virtuoso IC610自带的Stream Out导出版图库文件(GDS文件),并做了DRC、LVS等规则检查,完成版图库的设计。绘制低漏功耗单元的版图时,应严格遵照NCSU 45nm的工艺文件规则,以减少布局布线阶段的布线误差。例如,标准单元的高度要相同,高度宽度都要是金属与金属之间的最小间距(pitch)的整数倍,PIN要摆放在水平和垂直的布线通道的交汇处等等;3、对低漏功耗标准单元进行物理库和时序综合库的设计。使用Cadence公司的Abstract工具提取标准单元的物理抽象,包括金属层的距离和形状,PIN的位置等信息的提取,生成物理库。使用Liberty NCX和HSPICE实现标准单元的特征化,生成可逻辑综合的时序综合库;4、对低漏功耗标准单元包进行验证。利用所设计的低漏功耗CMOS标准单元包进行加法器和FIR滤波器的设计;完成了从逻辑综合到布局布线的后端设计,对所设计的低漏功耗CMOS标准单元包进行可用性和有效性验证。结果表明,本文所设计的低漏功耗CMOS标准单元包可以被主流的EDA工具调用,同时该低漏功耗CMOS标准单元包降低了电路的漏功耗,与NCSU 45nm标准单元库相比,4位串行加法器电路的漏功耗降低了9.50%,16阶FIR数字滤波器的漏功耗降低16.77%。另外FIR数字滤波器的电路面积也得到了3.27%的优化。
[Abstract]:With the rapid development of integrated circuits, the design process of VLSI has entered the nanometer scale. The decrease of threshold voltage of MOS devices makes the leakage current of the chip increase exponentially, resulting in the rapid increase of leakage power consumption. Leakage power has become an important part of the total power consumption. The function of standard cell in the design of digital ASIC integrated circuit is very important. Reducing the power consumption of standard cell will reduce the total power consumption of ASIC chip. In nanotechnology, reducing the leakage power of standard cells will directly affect the leakage power level of ASIC chips. Therefore, it is very important to study the low leakage power standard cell for the design of low leakage power ASIC chip. This paper introduces the leakage power reduction technology of CMOS circuit and the knowledge background of standard cell library building technology. In the NCSU 45nm process, a low leakage power standard cell package is constructed, which provides the basis for the design of low leakage power ASIC based on standard cell. The research of this paper is divided into the following parts: 1. The leakage power reduction technology under nanotechnology is studied and applied to the design of standard cell. The standard cell of NCSU 45nm process is analyzed by channel length modulation technique, and the transistor size of standard cell is optimized in order to reduce leakage power consumption. According to the optimized transistor size, the low leakage power design of common standard cells is carried out, which mainly includes standard cells such as combinatorial logic gates and flip-flop. Based on power control sleep technology, a new low leakage power master-slave D flip-flop structure with data retention function is proposed. The layout of low leakage power standard cell is drawn, and then the layout library file is exported by Stream Out of Virtuoso IC610, and the rule checking is done to complete the design of plate library. When drawing the layout of low leakage power unit, we should strictly follow the rules of NCSU 45nm process file, so as to reduce the routing error in layout and routing stage. For example, the height of a standard cell is the same, The height and width should be the minimum distance between metal and metal. The PIN should be placed at the intersection of horizontal and vertical wiring channels and so on. The physical library and time sequence synthesis library of low leakage power standard cell are designed. The physical abstraction of the standard unit is extracted by using Cadence's Abstract tools, including the extraction of the distance of metal layer and the position of the shape of the PIN, and the physical library is generated. Liberty NCX and HSPICE are used to realize the feature of the standard cell, and the logical synthesis time sequence synthesis library is generated, and the low leakage power standard cell package is verified. The low leakage power CMOS standard cell packet is used to design the adder and FIR filter, the back-end design from logic synthesis to layout and routing is completed, and the usability and validity of the designed CMOS standard cell package are verified. The results show that the low leakage power CMOS standard cell package designed in this paper can be called by the mainstream EDA tools, and the low leakage power CMOS standard cell packet can reduce the leakage power of the circuit. Compared with the NCSU 45nm standard cell library, the leakage power consumption of the 4-bit serial adder circuit is reduced by 16.777.The leakage power consumption of the 16-order FIR digital filter is reduced by 9.50th order. In addition, the circuit area of FIR digital filter is optimized by 3.27%.
【学位授予单位】：宁波大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN432

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