超高速采样保持电路的研究与设计

发布时间：2018-04-27 11:40

本文选题：超高速 + 采样保持电路　；参考：《合肥工业大学》2017年硕士论文

【摘要】：模数转换器(Analog-to-Digital Converter,ADC)作为模拟信号向数字信号转换的关键电路,广泛应用于现代通信、图像采集、医疗电子等众多领域。随着软件无线电和通信高频化的发展,ADC也朝着高速方向发展,因此超高速ADC的研究受到学术界的广泛关注。采样保持电路(Trcak and Hold Circuit,THC)位于超高速ADC的最前端,是十分重要的组成部分,其作用是将连续变化的模拟输入信号的瞬时值通过采样和保持转换为离散信号,并保持一段时间供后级核心电路进行量化和编码。因为THC位于ADC的最前端,因此其性能直接影响整个ADC的性能。如何在保证精度的情况下,尽可能提高THC采样速率是研究的关键。本文基于设计高速高精度折叠插值ADC的背景,选择开环架构来设计超高速THC,并针对开环THC架构的优缺点,研究影响速度和精度的关键点;分析非线性对电路性能的影响,并通过引入带有源极退化技术的级间缓冲器、高线性度的栅压自举开关以及虚拟开关吸收电荷注入等技术来提高THC的线性度;采用两通道时间交织架构提高THC的采样速率,并且针对两通道的失调失配,使用手动校准失调补偿技术来减小误差;采用全深N阱管的差分运放结构作为缓冲器;此外,还设计了供电模块给级间缓冲器供电以及电荷泵复位减小捕获时间。本文在Cadence Spectre环境下基于TSMC 0.18μm CMOS工艺设计和仿真电路,采用2V单电源供电。整体电路仿真结果表明,在1GSps的采样率下,采用相干采样,负载电容为预放大器寄生电容,输入800mVpp的正弦波,信号与噪声失真比(SNDR)达到 75.56dB,有效位数(ENOB)超过 12.25 位,达到了 12 位 1GSps ADC对于前端THC的性能要求。
[Abstract]:As the key circuit of analog to digital signal conversion, Analog-to-Digital converter (ADC) is widely used in many fields such as modern communication, image acquisition, medical electronics and so on. With the development of high frequency software radio and communication, the research of ultra high speed ADC has been paid more and more attention. Trcak and Hold circuit is a very important component of ultra-high speed ADC, which is used to convert the instantaneous value of continuously changing analog input signal into discrete signal by sampling and holding. And maintain a period of time for the core circuit after the quantization and coding. Because THC is at the front end of ADC, its performance directly affects the performance of the entire ADC. How to improve the sampling rate of THC as much as possible under the condition of ensuring precision is the key to the research. Based on the background of designing high speed and high precision foldable interpolated ADC, open loop architecture is chosen to design ultra high speed THC, and the key points that affect speed and precision are studied according to the advantages and disadvantages of open loop THC architecture, and the influence of nonlinearity on circuit performance is analyzed. The linearity of THC is improved by introducing interstage buffer with source pole degradation technology, high linearity gate voltage bootstrap switch and virtual switch absorption charge injection, and using two channel time interleaving architecture to improve the sampling rate of THC. Aiming at the mismatch of the two channels, the manual calibration offset compensation technique is used to reduce the error; the differential operational amplifier structure of the all-deep N-well tube is used as the buffer; in addition, The power supply module is designed to supply the interstage buffer and the charge pump reset to reduce the capture time. In this paper, based on TSMC 0.18 渭 m CMOS process design and simulation circuit in Cadence Spectre environment, 2V single power supply is used. The simulation results of the whole circuit show that under the sampling rate of 1GSps, the coherent sampling is used, the load capacitance is the parasitic capacitance of preamplifier, the sinusoidal wave of the input 800mVpp is input, the ratio of signal to noise distortion is 75.56 dB, and the effective bit ENOB is more than 12.25 bits. The performance requirements of 12 bit 1GSps ADC for front end THC are achieved.
【学位授予单位】：合肥工业大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN792

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