40nm工艺下流水线模数转换器关键单元的研究与设计

发布时间：2018-04-28 19:05

本文选题：40nm + 流水线模数转换器　；参考：《兰州大学》2015年硕士论文

【摘要】：Intel新一代处理器使用的是目前比较先进的14nm工艺,而国内芯片使用的工艺还普遍停留在0.13um、0.18um阶段。相对于TI等大公司,国内ADC芯片的水平较低,市场基本被国外公司垄断,国内芯片水平急需提升。本论文首先对流水线模数转换器中的关键单元进行了详细的计算推导,包括运算放大器需求的计算以及采样电容值的确定,并分析比较了三种结构的采样电路。之后,使用Matlab建模工具完成了流水线模数转换器的建模工作,不仅使各个模块的指标更加明确,并且为后期研究某一特定非理想因素对整体性能的影响提供了基础。本论文设计了两种结构的运算放大器以适应流水线模数转换器对运算放大器的不同需求。由于40nm工艺下供电电压较低、运算放大器增益需求较高、以及功耗等因素,运算放大器整体采用了两级折叠共源共栅结构,运算放大器的后仿结果能够达到：Gain为80.41dB, GBW为759.6MHz, PM为61.1。,功耗为7.2578mW。在非理想因素的处理方面,本论文主要研究的是电容的失配以及开关的非线性电阻两个方面。为了减小开关的非线性电阻,设计了自举开关替代普通开关,并对比了自举开关使用前后的效果。结合其他模块,本论文最终在SMIC 40nm CMOS工艺下完成了12bit/60Msps流水线模数转换器的设计,单通道整体后仿结果：SNDR为68.7dB, THD为-75.1dB, SFDR为74.6dB,有效位高达11.12bit,功耗为61.9mW。
[Abstract]:The current advanced 14nm process is used in the new generation of Intel processors, while the technology used in domestic chips is still generally in the 0.13um / 0.18um stage. Compared with TI and other large companies, the level of domestic ADC chips is relatively low, the market is basically monopolized by foreign companies, and the level of domestic chips needs to be improved urgently. In this paper, the key units of pipeline A / D converter are calculated and deduced in detail, including the calculation of operational amplifier requirements and the determination of sampling capacitance, and the analysis and comparison of three kinds of sampling circuits. After that, the modeling work of pipeline A / D converter is completed by using Matlab modeling tool, which not only makes the index of each module more clear, but also provides a foundation for the later study of the influence of a particular non-ideal factor on the overall performance. In this paper, two kinds of operational amplifiers are designed to meet the different requirements of pipeline A / D converters. Because of the low supply voltage in 40nm process, high gain requirement of operational amplifier and power consumption, the operational amplifier adopts a two-stage folded common-source common-gate structure. The post-simulation results of operational amplifier can reach 80.41 dB, GBW 759.6 MHz, PM 61.1.The power consumption is 7.2578 MW. In the aspect of dealing with non-ideal factors, this thesis mainly focuses on two aspects: capacitance mismatch and switch nonlinear resistance. In order to reduce the nonlinear resistance of the switch, the bootstrap switch is designed to replace the ordinary switch, and the effect of the bootstrap switch before and after the use of the bootstrap switch is compared. Combined with other modules, the design of 12bit/60Msps pipelined A / D converter in SMIC 40nm CMOS process is completed. The simulation results of single channel are as follows: SNDR is 68.7 dB, THD is -75.1 dB, SFDR is 74.6 dB, the effective bit is 11.12 bit and the power consumption is 61.9 MW.
【学位授予单位】：兰州大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN792

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