基于Encounter的RISC_CPU后端设计研究

发布时间：2018-04-29 18:56

本文选题：逻辑综合 + 可测性设计　；参考：《西安电子科技大学》2015年硕士论文

【摘要】：随着科技的进步与人们需求的不断提高,越来越多的高科技产品陆续的问世,而这些产品的出现大多数得益于集成电路技术的不断发展与进步。在半导体行业存在着一个摩尔定律,它预测芯片的集成度大概每十八个月左右就会增加一倍,规模的提高将要求工艺尺寸随之下降。工艺尺寸不断下降会使寄生效应变得更加严重,时序收敛难度增大。考虑到由寄生效应引起的信号完整性、动态电压降以及超高的集成度、GHz以上的频率,时序收敛问题仅仅靠工艺技术的提升是难以得到解决的。作为一名物理设计和实施工程师,其艰巨任务就是在这种条件下如何实现缩短芯片设计的周期,快速进入市场。因此,物理设计绝对不是仅仅熟悉后端设计的整个流程和熟练掌握EDA工具就可以的,它需要工程师对于设计目标的总体特征以及物理实现的方法都有充分透彻的理解。本文按照ASIC后端设计的流程,采用TSMC 0.18um 1P6M COMS工艺实现8位RSIC_CPU的后端设计,主要设计流程及研究结果如下:1.对逻辑综合理论的研究。逻辑综合是将具有一定功能的RTL级代码综合、映射成电路结构,本文重点研究了逻辑综合过程中如何对设计目标添加时序约束和工作环境的设置,与此同时,阐述了综合时对于多时钟域路径的时序约束的处理方法以及逻辑综合实现的过程和对于违例路径的优化方法。基于以上理论完成了8位RISC_CPU的时序约束的添加、工作环境的设置,实现了对该设计的逻辑综合,查看综合后的时序报告文件检验时序是否收敛,对设计目标的逻辑综合进行优化生成门级网表。最后利用Formality基于形式验证的方法对该设计的逻辑综合前后逻辑功能进行等价性检查,确保综合产生的网表文件与RTL级代码描述的逻辑功能是一致的。2.对可测性设计的研究。随着集成电路规模的发展,测试成本所占比重越发突出,为了降低设计过程中测试所耗费的成本,减小出现故障的几率,提高设计的质量和量产的成品率,可测性设计在芯片设计中得到广泛应用。本文介绍了可测性设计的基本理论知识和设计实践中常用的测试方法以及常见的故障类型,讨论了测试的设计规则,完成了8位RISC_CPU的扫描测试和故障测试,进行了测试覆盖率的检查,采用两种不同方法对设计进行优化,去除了测试中引脚不可控问题,提高测试覆盖率。最后在设计中插入了扫描链完成测试并对DFT后的时序进行分析。3.对静态时序分析的研究。论述了静态时序分析的基本原理,延时计算与参数提取的方法。对时序路径进行划分与时序分析,检查违例路径。介绍了常见的造成时序违例的因素及时序优化的方法。重点介绍了OCV条件下的时序分析以及共同路径悲观方法的相关内容,本文采用基于CPPR的方法完成了8位RISC_CPU的时序分析,保证时序满足时序约束的要求。4.对物理实现过程的研究。简述了数字后端设计的设计流程,研究了布图规划的内容以及其结果对后续设计时序的相关影响。在时钟树综合过程,采用了手动与自动相结合的方法完成了时钟树的综合,减小时钟叶节点之间的skew。最后,将routing后的网表与布图前的网表通过形式验证完成了一致性检查,确保物理实现前后设计的逻辑功能没发生改变。
[Abstract]:With the progress of science and technology and the increasing demand of people, more and more high-tech products have come out in succession. Most of these products are due to the continuous development and progress of integrated circuit technology. There is a Moore law in the semiconductor industry, which predicts the integration of chips will increase about every eighteen months. The increase in scale will require a decrease in the size of the process. The continuous decline in the process size makes the parasitic effect more serious and the time series converges more difficult. Considering the signal integrity, dynamic voltage drop, and ultra high integration, the frequency of GHz above the frequency of the parasitism, the problem of time series convergence is only dependent on the improvement of technology technology. It is difficult to solve the problem. As a physical design and Implementation Engineer, the difficult task is how to shorten the cycle of chip design under this condition and quickly enter the market. Therefore, the physical design is absolutely not only familiar with the whole process of the back end design and the skillful mastery of the EDA tool. It requires engineers to set up the design. The overall characteristics of the target and the method of physical realization are fully understood. According to the process of the ASIC backend design, this paper uses the TSMC 0.18um 1P6M COMS process to realize the back end design of 8 bit RSIC_CPU. The main design process and the results are as follows: 1. the study of the logic synthesis theory. Logic synthesis is a RTL with a certain function. The level code is integrated and mapped into the circuit structure. This paper focuses on how to add the timing constraints and the setting of work environment to the design target in the logic synthesis process. At the same time, the process of dealing with the time sequence constraints of the multi clock domain path, the process of logical synthesis and the optimization method for the violation path are expounded. Based on the above theory, the time sequence constraints of the 8 bit RISC_CPU are added, and the setting of the working environment has realized the logical synthesis of the design. The test sequence of the time series report files after the synthesis is convergent, and the logic synthesis of the design target is optimized to generate the gate level net table. Finally, the method based on the formal verification of Formality is used. The logic function of the integrated logic integrated before and after the design is checked to ensure that the integrated network table file and the logic function of the RTL level code description are the same.2. for the measurable design. With the development of the integrated circuit scale, the proportion of the test cost is more prominent, and the cost of reducing the test in the design process is reduced and the cost is reduced. The probability of small failure, improving the quality of design and yield of product, is widely used in the design of chip. This paper introduces the basic theory of testability design, the common test methods and common fault types in the design practice, and discusses the design rules of the test and completes the 8 bit RISC_CPU scan. Test and fault test, test coverage rate, use two different methods to optimize the design, remove the pin uncontrollable problem in the test, improve the test coverage. Finally, in the design, the scan chain is inserted to complete the test and the time sequence analysis after DFT is analyzed. The static time sequence analysis is discussed. The static time is discussed. The basic principle of sequence analysis, the method of time delay calculation and parameter extraction. The time sequence path is divided and time series analysis, and the violation path is checked. The method of time sequence optimization is introduced. The time sequence analysis and the related content of the common path pessimistic method are introduced. The base of this paper is based on the OCV condition. In the method of CPPR, the time sequence analysis of 8 bit RISC_CPU is completed to ensure that the time sequence satisfies the requirement of time series constraints and the study of the physical realization process. The design process of the digital back end design is introduced, the content of the layout planning and the related effects on the sequence of the subsequent design are studied. The manual and self use are adopted in the clock tree synthesis process. The combination of moving phase completes the synthesis of clock tree, reduces the skew. between hourly clock and leaf nodes, and completes the consistency check by verifying the net table after routing and the network table before the layout, ensuring that the logic function of the design before and after the physical implementation has not changed.

【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN402

【参考文献】