用于超快光计时的时间数字转换器

发布时间：2018-05-02 11:07

  本文选题：延迟锁定环 + 时间数字转换电路　； 参考：《半导体光电》2017年03期

【摘要】：设计了一款基于延迟锁定环(DLL)和同步计数器结构的10位片上时间数字转换电路(TDC)。采用两步层级设计方法,利用同步计数器进行粗量化输出6位二进制码,量化时钟周期的整数倍,再利用高性能差分DLL输出16路固定相移的时钟信号采样,精量化不足一个时钟周期的部分,输出4位温度计码。该结构可以提供较好的精度、动态范围以及转换速度,与传统的子门延时TDC相比,该结构TDC占用的芯片面积更少,转换速度更高,受工艺、电压及温度影响更少。仿真结果表明:该TDC具有LSB 62.5ps和MSB 64ns的动态范围,满足一般与时间相关的单光子计数需要。
[Abstract]:A 10-bit time-to-digital conversion circuit based on DLL) and synchronous counter is designed. In this paper, a two-step hierarchical design method is used to output 6-bit binary code by using synchronous counter, which quantizes the integer times of clock cycle, and then outputs 16-channel fixed phase-shift clock signal sampling by using high performance differential DLL. Precision quantization of less than one part of the clock cycle, output 4-bit thermometer code. The structure can provide better precision, dynamic range and conversion speed. Compared with the traditional sub-gate delay TDC, the structure TDC occupies less chip area, has higher conversion speed and is less affected by technology, voltage and temperature. The simulation results show that the TDC has the dynamic range of LSB 62.5ps and MSB 64ns, which can meet the needs of time dependent single photon counting.
【作者单位】： 天津大学仁爱学院;天津职业技术师范大学电子工程学院;天津力神电池股份有限公司;
【分类号】：TN402
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本文编号：1833620