S波段射频LDMOS晶体管的设计与实验研究

发布时间：2018-05-02 23:47

本文选题：射频LDMOS + Trench　；参考：《电子科技大学》2015年硕士论文

【摘要】：现代移动通信的飞速发展,对信息传输的高质,高量推动了射频LDMOS向更高的频率和更宽的带宽应用,同时也给设计技术带来了严峻的挑战。由于国内射频LDMOS研发能力与国外存在不小差距,开展LDMOS的研究和设计对国防和国民经济有重要意义。本论文主要针对S波段射频LDMOS器件进行设计和建模。LDMOS器件结构采用了单层Shield源极场板;源极有源区采用减小器件面积的Trench sinker结构。基于该结构进行了仿真设计与部分结构参数的优化。并用Cadence绘制了器件版图,在上海华虹宏力半导体公司进行流片实验。对栅长0.4μm,栅宽140μm的器件得到饱和电流210mA/mm,击穿电压65V,阈值电压1.5V,截止频率9GHz。对栅宽1mm的器件,获得3dB增益压缩功率30.1dBm,最大增益20.1dB以及最大效率53.1%,功率密度达到1W/mm。最后基于测试数据,采用Angelov非线性模型对栅长0.4μm,栅宽140μm的LDMOS器件进行了模型分析。其中在直流IV模型拟合时,将拟合因子P1与漏压Vds关联,得到了较好的拟合结果。在非线性电容模型分析中,测试的漏源电容Cds发现其受偏压影响较大,因此,同时对Cds、Cgs和Cgd进行了模型拟合。最后将建立的模型嵌入到ADS中,得到了小栅宽器件的大信号模型。本论文通过器件设计仿真,测试获得了性能较好的RF LDMOS器件。并建立了双栅指小栅宽器件的大信号模型,为以后对大栅宽大功率RF LDMOS器件的建模奠定了良好的基础。
[Abstract]:With the rapid development of modern mobile communication, the high quality and high quantity of information transmission promote the application of RF LDMOS to higher frequency and wider bandwidth. At the same time, it also brings a severe challenge to the design technology. Because of the gap between domestic RF LDMOS R & D capability and foreign countries, the research and design of LDMOS is of great significance to national defense and national economy. In this paper, we design and model the S-band RF LDMOS devices. The single-layer Shield source polar field board is used in the device structure, and the Trench sinker structure is used to reduce the device area in the source region. Based on this structure, simulation design and optimization of some structural parameters are carried out. The device layout was plotted by Cadence, and the flow sheet experiment was carried out in Shanghai Huahong Hongli Semiconductor Company. For devices with a gate length of 0.4 渭 m and a gate width of 140 渭 m, a saturation current of 210 Ma / mm, a breakdown voltage of 65 V, a threshold voltage of 1.5 V and a cut-off frequency of 9 GHz were obtained. For the devices with wide gate width 1mm, the gain compression power of 3dB is 30.1dBm, the maximum gain 20.1dB and the maximum efficiency 53.1. The power density is up to 1W / mmm. Finally, based on the test data, the Angelov nonlinear model is used to model the LDMOS devices with a gate length of 0.4 渭 m and a gate width of 140 渭 m. When fitting DC IV model, the fitting factor P1 is correlated with leakage pressure Vds, and a good fitting result is obtained. In the analysis of nonlinear capacitance model, the measured drain source capacitance (Cds) is found to be greatly affected by bias voltage. Therefore, the model fitting of CDs CGS and Cgd is carried out at the same time. Finally, the model is embedded into ADS, and the large signal model of small gate width device is obtained. In this paper, RF LDMOS devices with good performance are obtained through device design and simulation. The large signal model of double gate finger small gate width device is established, which lays a good foundation for the modeling of large gate wide and high power RF LDMOS device in the future.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN386

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