基于MEMS传感器的姿态解算的FPGA实现

发布时间：2018-05-03 06:08

本文选题：姿态解算 + MEMS惯性器件　；参考：《长沙理工大学》2015年硕士论文

【摘要】：目前的姿态测量系统中的姿态解算大部分基本上是使用单片机、ARM、DSP、或者FPGA里的软核处理器及硬核处理器等来实现,在处理的速度上受到一定的限制,一些处理过程不能同时进行,影响到姿态解算的速度。本文主要对姿态解算的全数字逻辑实现方式进行了研究,提出了一种利用FPGA来进行姿态解算的实现方案,希望可以提高姿态解算的处理速度及数据的可靠性。本设计利用FPGA的硬件结构,实现并行和流水线等结构;根据FPGA的数字逻辑特性,选择了比较合适的姿态解算实现方式。主要包括:传感器数据采集电路部分、信息融合部分、姿态解算部分、上位机通信等部分。通过对比互补滤波和卡尔曼滤波两种数据融合方法的优缺点,并根据FPGA的数字逻辑的特点选择了互补滤波的滤波方法;采用流水线的结构来实现CORDIC算法,提高了计算速度;确定了使用四元数来实现姿态解算,提高了解算的准确性和开发效率;结合互补滤波算法和四元数法对传感器数据进行了处理并实现FPGA与上位机通信。通过逻辑分析仪和串口调试助手等工具对设计的正确性进行了验证、测试,结果表明本设计能基本完成姿态解算的目标,有一定的理论和实践价值。
[Abstract]:Most of the attitude resolution in the present attitude measurement system is realized by using single chip microcomputer (SCM) DSP, or soft core processor and hard core processor in FPGA. The processing speed is limited, and some processing processes cannot be carried out at the same time. Affects the speed of attitude resolution. In this paper, the full digital logic implementation of attitude resolution is studied, and a scheme of attitude resolution using FPGA is proposed. It is hoped that the processing speed of attitude resolution and the reliability of the data can be improved. The hardware structure of FPGA is used to realize parallel and pipelined structure, and according to the digital logic characteristic of FPGA, a more suitable way of attitude calculation is selected. It mainly includes: sensor data acquisition circuit, information fusion, attitude calculation, host computer communication and so on. By comparing the advantages and disadvantages of two data fusion methods, complementary filtering and Kalman filtering, and according to the characteristics of digital logic of FPGA, the filtering method of complementary filtering is selected, the pipeline structure is used to realize CORDIC algorithm, and the calculation speed is improved. It is determined to use quaternion to realize attitude calculation, to improve the accuracy and development efficiency of the solution, to process the sensor data with complementary filtering algorithm and quaternion method, and to realize the communication between FPGA and host computer. The correctness of the design is verified by means of logic analyzer and serial port debugging assistant. The results show that the design can basically accomplish the goal of attitude calculation and has certain theoretical and practical value.
【学位授予单位】：长沙理工大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN791;TH-39;TP212

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