基于FPGA的低延迟数据传输设计

发布时间：2018-05-06 01:32

本文选题：低延迟 + 硬件加速　；参考：《郑州大学》2017年硕士论文

【摘要】：随着万兆以太网的出现,链路中海量的数据传输对金融交易系统产生了巨大压力,传统的基于软件或以软件为核心的硬件加速技术已经不能满足服务器低延迟传输的需求。因此,迫切需要找到一种能满足数据实时传输的解决方案。经查阅相关资料,采取既能满足高效传输需求又能灵活配置的硬件加速平台是解决问题的关键。在方案设计时,本文以网卡接收网络数据包到把数据存入到主机内存中的过程作为设计的对象。采用一种简化的设计方案,将传输过程中耗时较多的TC P/IP协议栈和加解密运算从处理器的操作下释放出来,用硬件平台实现,以实现数据的低延迟传输。最后对方案进行测试,用实际测试结果验证设计的合理性。根据以上情况,本文提出了一种基于FPGA的低延迟传输方案,将TCP/IP协议栈处理和加密运算的过程在FPGA平台上实现,并采用高速总线技术实现F PGA平台和服务器之间数据的高速传输。其中,TCP/IP协议栈的处理由TCP/IP卸载引擎IP核实现,加解密过程采用DES模块实现,高速总线采用PCI-E接口总线。设计采用Xilinx公司的Vivado软件作为开发环境,以Modelism作为波形仿真工具。测试结果表明:DES模块的硬件实现速率能够达到16Gbps,延迟为64ns,PCI-E接口模块的DMA读写速率分别为318MB/s和476MB/s,延时为750ns,TOE核的延迟为190ns,系统总延迟为1.1us,系统的功耗为2.926W。与软件方案相比,硬件方案在功耗和延迟上都有较大的优势,具有很好的应用前景。
[Abstract]:With the emergence of Gigabit Ethernet, the massive data transmission in the link has brought great pressure to the financial transaction system. The traditional hardware acceleration technology based on software or software as the core can no longer meet the demand of low delay transmission of server. Therefore, there is an urgent need to find a solution to meet the real-time data transmission. The key to solve the problem is to adopt a hardware acceleration platform which can meet the needs of efficient transmission and can be configured flexibly. In the design of the scheme, the process that the network card receives the network data packet and stores the data into the host memory is taken as the design object. In this paper, a simplified design scheme is adopted, which releases the TC P/IP stack and encryption and decryption operation from the operation of the processor during the transmission process, and realizes the data transmission with low delay on the hardware platform. Finally, the scheme is tested, and the rationality of the design is verified by the actual test results. According to the above situation, this paper proposes a low delay transmission scheme based on FPGA, which realizes the process of processing and encrypting the TCP/IP protocol stack on the FPGA platform. High-speed bus technology is used to realize high-speed data transmission between F PGA platform and server. The processing of TCP / IP stack is implemented by the IP core of TCP/IP unload engine, the encryption and decryption process is implemented by DES module, and the high-speed bus is implemented by PCI-E interface bus. The design adopts the Vivado software of Xilinx Company as the development environment and Modelism as the waveform simulation tool. The test results show that the hardware implementation rate of the 1: DES module can reach 16 Gbpss, the DMA reading and writing rate of the 64nsOP-PCI-E interface module is 318MB/s and 476MB / s, the delay is 190nsof 750nstoe core, the total delay of the system is 1.1usand the power consumption of the system is 2.926w. Compared with the software scheme, the hardware scheme has great advantages in power consumption and delay, and has a good application prospect.
【学位授予单位】：郑州大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN919.6;TN791

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