LDPC码高效编译码器设计与FPGA实现

发布时间：2018-05-06 11:11

本文选题：低密度奇偶校验码 + 低存储编译码器　；参考：《河北大学》2015年硕士论文

【摘要】：随着现代数字通信系统的飞速发展,低密度奇偶校验码(Low-Density Parity-Check)即LDPC码凭借其具有逼近香农(Shannon)极限的性能以及低复杂度的译码算法和高并行度的硬件实现架构成为了近年来信道纠错编码技术研究的重点。本文深入研究了基于FPGA的LDPC码高效低存储量编译码器的实现方法。论文的主要工作包括:研究LDP C码的编译码算法及并利用Matlab仿真软件完成校验矩阵的构造,对多种编译码算法进行仿真比较,最终完成高效LDPC码编译码器的FPGA实现。本文首先介绍了LDPC码的基本概念和国内外发展现状,并通过对LDPC码的分类和表示方法的介绍引出LDPC码中的一类特殊码型——准循环低密度奇偶校验码(Quasi Cyclic-LDPC码),QC-LDPC码结合了结构性和随机性的特点,在保证LDPC码的信道性能不变的情况下,大大减小了编码算法的复杂程度,被广泛应用在众多数字通信系统当中。其次,本文通过Matlab仿真,实现了LDPC码校验矩阵的不同构造方法,经过多次仿真测试分析各种构造方式的优缺点。然后系统的分析和总结LDPC码的编译码方法,对传统译码算法和快速编码算法进行比较,并详细推导了LDPC码在高斯白噪声信道下置信传播译码算法的消息更新规则,以及由其演化而来的对数似然比译码算法和最小和译码算法,通过综合分析确定快速编码算法及最小和译码算法作为高效LDPC码编译码器的基本设计思想。最后,本文根据快速编码算法,选取基于IEEE 802.16e标准的校验矩阵,只存储基矩阵中每个子矩阵的首地址,并通过正向反向双向递归计算校验位。设计了一种高效低存储的LDPC码编码器,节省了FPGA逻辑资源开销并提高了编码速度。而译码器的设计则根据最小和译码算法,变量节点和校验节点的更新均采用块间并行、块内串行的方式进行。该方案可有效降低译码器对硬件存储空间的占用,并降低了译码电路的布线复杂度。
[Abstract]:With the rapid development of modern digital communication system, Low-Density Parity-Check (LDPC) codes have become the focus of research on channel error correction coding in recent years because of their performance of approaching Shannon's limit, low complexity decoding algorithm and high parallelism hardware implementation architecture. In this paper, the implementation of efficient low memory codec of LDPC code based on FPGA is studied. The main work of this paper is as follows: the coding and decoding algorithm of LDP C code is studied and the construction of check matrix is completed by using Matlab simulation software. Finally, the FPGA implementation of efficient LDPC codec is finished by comparing and simulating various encoding and decoding algorithms. In this paper, the basic concept of LDPC code and its development status at home and abroad are introduced. By introducing the classification and representation of LDPC codes, a class of special codes in LDPC codes, quasi low density parity check codes, QC-LDPC codes, are introduced. The QC-LDPC codes combine the characteristics of structure and randomness. Under the condition that the channel performance of LDPC code is invariable, the complexity of the coding algorithm is greatly reduced, and it is widely used in many digital communication systems. Secondly, through Matlab simulation, different construction methods of LDPC code check matrix are realized, and the advantages and disadvantages of various construction methods are analyzed through several simulation tests. Then the encoding and decoding methods of LDPC codes are systematically analyzed and summarized. The traditional decoding algorithms and fast coding algorithms are compared, and the message updating rules of confidence propagation decoding algorithm for LDPC codes in Gao Si white noise channel are deduced in detail. The logarithmic likelihood ratio decoding algorithm and the minimum sum decoding algorithm derived from the algorithm are analyzed. The fast coding algorithm and the minimum sum decoding algorithm are determined as the basic design ideas of the efficient LDPC codec. Finally, according to the fast coding algorithm, this paper selects the check matrix based on IEEE 802.16e standard, only stores the first address of each submatrix in the base matrix, and calculates the check bit by forward reverse bidirectional recursion. An efficient and low storage LDPC encoder is designed, which saves the FPGA logic resource overhead and improves the coding speed. On the other hand, the decoder is designed according to the minimum sum decoding algorithm. The update of variable node and check node is carried out in parallel between blocks and serial within blocks. This scheme can effectively reduce the storage space of the decoder and reduce the routing complexity of the decoding circuit.
【学位授予单位】：河北大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN911.22;TN791

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