电源芯片漏电流失效分析及良率提升研究

发布时间：2018-05-07 20:38

本文选题：电源管理芯片 + 漏电流　；参考：《大连理工大学》2015年硕士论文

【摘要】：电源管理芯片是每部移动电子设备不可或缺的部分,它直接影响着移动电子设备的功耗和待机时间。在设计和制造工艺交互作用下产生的缺陷所造成的漏电流失效是制约电源管理芯片产品良率的主要因素。在芯片能够批量上市之前,它首先必须达到能以可接受的良率(Yield)进行批量制造的水平。但从集成电路设计到工艺制造存在一个良率逐步提升的过程,需要一定的时间。芯片的设计验证完成时间还要再加上这个良率时间才是真正的产品上市时间,因此良率的快速提升成为集成电路芯片设计公司打开市场,获得利润的迫切要求。本文选取一款市面在用的移动电子设备上的电源管理芯片开展漏电流失效分析及良率提升研究。在数据分析方面,抽样出100片晶圆,对它的漏电流针测(Chip Probe, CP)并对采样数据采用累积叠加分布的方式制作分布图。在电性分析方面,采用4156C(精密半导体参数分析仪)测量I-V曲线,采用红外发光显微镜(Emission Microscopy, EMMI)和激光诱导电阻率变化测试仪(Optical Beam Induced Resistance Change, OBIRCH)定位缺陷位置。然后用原子力显微镜(Atomic Force Microscopy, AFM)和纳米探针系统(NanoProbe)分析失效模式。在物理分析方面,采用物理剥层、聚焦离子束显微镜(Focused Ion Beam, FIB)、扫描电镜(Scanning Electron Microscope, SEM)、缺陷化学成分分析和电压衬度(Voltage Contrast, VC)定位技术来建立失效模型。通过研究,找到了该芯片的失效根源,配合生产线研究失效的产生机理,找出了良率提升的办法。
[Abstract]:Power management chip is an indispensable part of every mobile electronic device. It directly affects the power consumption and standby time of mobile electronic device. The leakage current failure caused by the defects caused by the interaction of design and manufacturing process is the main factor that restricts the yield of power management chip products. Before the chip can be mass-produced, it must first reach the level of mass manufacturing with acceptable yield yield. However, from IC design to process manufacturing, there is a process of increasing yield, which will take a certain amount of time. The completion time of chip design verification must be coupled with this yield time which is the real time to market. Therefore, the rapid improvement of yield becomes the urgent requirement for IC chip design companies to open up the market and make profits. In this paper, a power management chip for mobile electronic devices in use is selected to study leakage current failure and yield enhancement. In the aspect of data analysis, 100 wafers are sampled, and its leakage current needle is used to measure Chip Probe (CPP), and the distribution map is made by accumulative superposition distribution of the sample data. The I-V curve was measured by 4156C (Precision Semiconductor Parameter Analyzer), and the defect position was located by infrared luminescence microscope (EMMI) and laser-induced resistivity change tester (Beam Induced Resistance Change, OBIRCH). Then atomic Force microscopy (AFM) and nanometer probe system (Nano Probe) were used to analyze the failure mode. In terms of physical analysis, failure models were established by physical stripping, focusing ion beam microscope, focused Ion beam, scanning electron microscopy, scanning Electron microscope, SEMU, defect chemical composition analysis and voltage contrast (VC) localization techniques. Through the research, the cause of failure of the chip is found, and the mechanism of the failure is studied with the production line, and the method of improving the yield is found.
【学位授予单位】：大连理工大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN405

【参考文献】