小数分频频率合成器相位噪声建模研究

发布时间：2018-05-12 03:37

本文选题：小数分频频率合成器 + 电荷泵　；参考：《西南科技大学》2015年硕士论文

【摘要】：在DCS-1800系统中,小数分频频率合成器的输出相位噪声能达到-116dBc/Hz@600k,Hz-133dBc/Hz@3MHz。而在一篇文献报道中针对DCS-1800系统,设计出一种新型小数分频频率合成器输出相位噪声小于-124dBc/Hz@600kHz和-142dBc/Hz@3MHz。但在该文献中并没有对这种新型小数分频频率合成器输出相位噪声得到明显改善的原因进行深入研究。因此,分析和研究新型小数分频频率合成器减小输出相位噪声的原因有重要的实际意义。本文针对一种新型小数分频频率合成器的相位噪声展开研究,在明确其系统结构及其关键功能模块工作原理的基础上,重点研究了在实际工作状态下电荷泵和鉴频鉴相器的相位噪声机理及其建模方法。其中,本文研究的电荷泵相位噪声机理包括:不同模式输入控制信号下电荷泵相位噪声、电荷泵非线性(电流增益不匹配和电流动态不匹配)引发的相位噪声。研究的鉴频鉴相器相位噪声机理包括:计时抖动引发的鉴频鉴相器相位噪声;鉴频鉴相器复位延迟不匹配引发的相位噪声。为了验证本文所建立的电荷泵和鉴频鉴相器的相位噪声模型的有效性,本文通过在MATLAB进行仿真计算和实验数据分析的基础上,并结合其他功能模块经典的、完备的相位噪声模型,对新型小数分频频率合成器系统进行了ADS行为级的仿真验证,并与文献数据进行比较,验证了模型的有效性。
[Abstract]:In DCS-1800 system, the output phase noise of fractional frequency division synthesizer can reach -116dBc / Hzr / Hz600kv Hz-133dBcP / HzBcr 3MHz. A novel fractional frequency synthesizer with phase noise less than -124dBc / Hzr / Hz@ 600kHz and -142dBc / Hzr @ Hzr 3MHz was designed in a literature report for DCS-1800 system. However, the reasons for the obvious improvement of the output phase noise of the new fractional frequency synthesizer have not been studied in this paper. Therefore, it is of great practical significance to analyze and study the reasons for reducing the output phase noise of the new fractional frequency divider. In this paper, the phase noise of a new type of fractional frequency synthesizer is studied. On the basis of clarifying the system structure and the working principle of the key function modules, the phase noise of a new type of fractional frequency synthesizer is studied. The phase noise mechanism and modeling method of charge pump and phase discriminator are studied in detail. The mechanism of charge pump phase noise studied in this paper includes: charge pump phase noise under different mode input control signals and phase noise caused by charge pump nonlinearity (current gain mismatch and current dynamic mismatch). The phase noise mechanism of phase discriminator includes phase noise caused by timing jitter and phase noise caused by mismatch of reset delay of phase discriminator. In order to verify the validity of the phase noise model of the charge pump and frequency discriminator, this paper is based on the simulation of MATLAB and the analysis of experimental data, combined with the classical model of other functional modules. Based on the complete phase noise model, the ADS behavior level simulation of the new fractional frequency division frequency synthesizer system is carried out, and the validity of the model is verified by comparing with the literature data.
【学位授予单位】：西南科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN74

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