纳米CMOS集成电路单粒子多瞬态效应及其抑制

发布时间：2018-05-13 08:40

本文选题：纳米CMOS集成电路 + 单粒子多瞬态　；参考：《国防科学技术大学》2015年博士论文

【摘要】：伴随着我国航天工业和航天活动的不断成长,抗辐照集成电路相关研究经历了从无到有,从弱到强的发展历程,空间辐射效应以及集成电路抗辐照设计已成为学术界和工业界的研究热点和难点。近年来,航天应用不断向高精尖迈进,其对数据、图像处理的需求急剧增长,这使得航天应用中采用先进纳米工艺成为必然。然而,纳米尺度下,器件集成密度急剧上升,电路工作频率上升,电路工作电压下降,使得单粒子瞬态(SET)的产生与传播变得更加复杂,单粒子多瞬态(SEMT)成为SET的常态,软错误(SER)发生的概率明显上升。本文着眼于单粒子多瞬态(SEMT)研究,基于“SEMT产生与传播机理?SEMT实验表征?SEMT抑制”这条主线,对纳米集成电路中单粒子多瞬态进行了多角度揭示,主要表现如下四个方面:(1)研究了同一路径上单粒子多瞬态脉冲的相互作用,发现纳米工艺下同一路径上多个晶体管可能产生2个以上的隐式单粒子瞬态脉冲,这些脉冲存在相互叠加的现象,进而诱发单粒子瞬态脉冲压缩(PQ)效应和单粒子瞬态脉冲窄后宽(PBAN)效应。不同工艺节点的Geant4模拟表明,工艺尺寸的缩减使得PQ和PBAN效应的发生概率持续增加;而在22纳米工艺节点下,同一路径上离输入最近的晶体管上产生的SET有60%的概率发生脉冲PQ效应,且这些被压缩的SET又有30%的概率再次被展宽。(2)研究了时序逻辑中非存储节点上单粒子多瞬态脉冲产生规律,发现了纳米工艺下触发器数据输入和时钟输入上产生的单粒子双瞬态诱发单粒子翻转机制。所设计的65nm双阱工艺测试芯片相关重离子实验结果不仅证实了该机制的存在,还首次表明了65nm工艺节点下该新型机制对单粒子翻转的贡献可能超过10%。同时,不同工艺尺寸的模拟表明,工艺尺寸的缩减使得SEMT诱发翻转所需的能量阈值降低。(3)研究了组合逻辑中通用单粒子多瞬态的测试方法,发现基于标准单元中任意单元构成纵向链阵列可以较好地实现组合逻辑中SEMT的产生,而将传统SET脉冲测量电路进行组合设计为SEMT脉冲测量电路即可对产生的SEMT进行在线捕获。本文基于反相器构成了的链阵列为UniVIC测试结构,并在65nm双阱和三阱工艺下生产出测试芯片。相关重离子实验结果表明:a)、在LET≤40 MeV?cm2/mg的辐射条件下,65纳米工艺下单粒子轰击最多影响3个晶体管,也就是最多产生单粒子三瞬态(SETT);b)、双阱结构下电荷共享诱发SEMT的概率不超过30%,而诱发SEMT时平均电荷共享强度达到80%~90%;c)、三阱结构下电荷共享诱发SEMT的概率显著提高到了约55%,但是诱发SEMT时平均电荷共享强度却减小到75%~80%。(4)研究了纳米工艺下SEMT的抑制技术,提出了镜像法和无缝保护带技术,并提出了单元级加固思想。该思想指出在标准单元中运用SET/SEMT加固技术可以有效降低电路的SER,且基于标准单元电路特征可对不同单元采用不同方式的SET/SEMT加固。本文提出的镜像法主要适用于具有两级级联结构的标准单元(如与非门),它通过增强前级和后级的电荷共享来强化前后两级产生的单粒子双瞬态(SEDT)相互抵消,进而抑制了单元末端SET的脉冲宽度。模拟结果表明:当前级PMOS处于关断状态时,镜像法能将末端SET消减超过25%;当前级PMOS处于开态时,镜像法能将末端SET消减约10%。而无缝保护带技术则主要适用于简单标准单元。模拟结果表明,65nm工艺节点下,对于入射能量小于40 MeV?cm2/mg的入射粒子,无缝保护带技术能彻底消除SEMT的产生,并且产生的SET脉冲宽度可减少约50%。本文之前关于电荷共享的研究数以百计,然而除时序逻辑MCU的研究较为清晰之外,组合逻辑中SEMT产生和传播以及最终对SER的影响涉及较少。一方面,本文改进了SEMT测量方法,首次提出了通用的SEMT测量方法,能适用于任意标准单元间SEMT产生分布的测量,也能适用于更先进工艺下SEMT产生分布的测量。另一方面,本文在前人的基础上对SEMT的产生与传播进行了有限地揭示,并提出了有效可行的SEMT抑制技术,这对指导纳米尺度下SER评估与预测提供了原始数据,有利于提高SER评估精度;也为抗辐照纳米集成电路设计提供了更为可靠的指导。
[Abstract]:With the continuous growth of space industry and space activities in China, the related research of anti radiation integrated circuits has experienced the development course from scratch, from weak to strong. Space radiation effect and integrated circuit anti radiation design have become the hot and difficult points in the academic and industrial circles. The demand for data and image processing has increased dramatically, which makes it inevitable to use advanced nanotechnology in space applications. However, the density of the devices is rising rapidly, the frequency of circuit work is rising, and the working voltage of the circuit is falling, which makes the generation and propagation of single particle transient (SET) more complex, single particle and multiple transient (SEMT). For the normal state of SET, the probability of the occurrence of soft error (SER) is obviously rising. This paper focuses on the single particle transient (SEMT) study. Based on the main line of "SEMT generation and propagation mechanism, SEMT experimental characterization? SEMT suppression", the multiple angles of single particle transient in nanoscale integrated circuits are revealed in many angles, mainly in the following four aspects: (1) the same one is studied. The interaction of single particle multi transient pulses on the path shows that more than 2 transistors on the same path in the nanotechnology may produce more than 2 implicit single particle transient pulses. These pulses have the phenomenon of overlapping each other, and then induce the single particle transient pulse compression (PQ) effect and the single particle transient pulse narrow after width (PBAN) effect. The Geant4 simulation of the art node shows that the reduction of the process size makes the probability of the PQ and PBAN effects increase continuously; and under the 22 nanotechnology node, the SET produced on the nearest transistor on the same path has a probability of 60% pulse PQ effect, and the probability of these compressed SET has a 30% probability to be broadened again. (2) a study was made. The rule of single particle transient pulse generation on a non storage node in sequential logic is found. The single particle double transient induced single particle flip mechanism is found in the data input of the trigger and the clock input in the nanotechnology. The experimental results of the related heavy ion of the 65nm double well process test chip not only confirm the existence of this mechanism, but also the first table. It is clear that the contribution of the new mechanism to single particle flipping may exceed 10%. at the same time in the 65nm process node. The simulation of different process sizes shows that the reduction of the process size makes the energy threshold of the SEMT induced turn down. (3) the testing method of the single particle multi transient in the combinational logic is studied, and it is found that any single single particle in the standard unit is based on any single. The formation of SEMT in combinatorial logic can be achieved by the composition of the longitudinal chain array, and the traditional SET pulse measurement circuit is designed as a SEMT pulse measurement circuit to capture the generated SEMT online. In this paper, the chain array composed of the inverters is a UniVIC test node and produced under the 65nm double well and three well process. Test chip. The results of related heavy ion experiments show: a), under the radiation condition of LET < 40 MeV? Cm2/mg, the single particle bombardment under 65 nanometers is most influential to 3 transistors, that is, the maximum generation of single particle three transient (SETT) and b). The probability of the charge sharing induced SEMT under the double well structure is not more than 30%, and the average charge sharing intensity of SEMT is induced. 80%~90%; c), the probability of charge sharing induced SEMT in the three well structure increased to about 55%, but the average charge sharing intensity decreased to 75%~80%. (4) when SEMT was induced, and the inhibition technology of SEMT under the nanotechnology was studied. The mirror image method and the seamless protective belt technology were proposed, and the unit level strengthening thought was put forward. The use of SET/SEMT reinforcement in the unit can effectively reduce the SER of the circuit, and based on the characteristics of the standard unit circuit, the different units can be reinforced by different ways of SET/SEMT reinforcement. The image method proposed in this paper is mainly applied to the standard unit with two cascade structures (such as NAND gate), which is strong by increasing the charge sharing of the front and rear stages. The single particle double transient (SEDT) produced before and after the two stages counteracts each other and inhibits the pulse width of the terminal SET at the end of the unit. The simulation results show that the mirror method can reduce the end SET by more than 25% when the current level PMOS is in the turn off state; when the current stage PMOS is in open state, the mirror method can reduce the end SET about 10%. and the seamless protective belt technology is main. It is suitable for simple standard units. The simulation results show that under the 65nm process node, for the incident particles with incident energy less than 40 MeV? Cm2/mg, the seamless protective band technology can completely eliminate the production of SEMT, and the generated SET pulse width can reduce the number of hundreds of studies on charge sharing before this article, but except the temporal logic MCU In addition to the clearer research, the SEMT generation and propagation in combinatorial logic and the influence of the final SER are less involved. On the one hand, this paper improves the SEMT measurement method and proposes the general SEMT measurement method for the first time. It can be applied to the measurement of SEMT production distribution between arbitrary standard units, and can also be applied to the measurement of SEMT production distribution under the more advanced technology. On the other hand, on the basis of the predecessors, the generation and propagation of SEMT have been limited, and the effective and feasible SEMT suppression technology is proposed. This provides the original data for guiding the evaluation and prediction of SER in the nanometer scale, and is helpful to improve the accuracy of the evaluation of the SER, and also provides a more reliable reference for the design of the anti irradiance nanoscale integrated circuits. Guide.

【学位授予单位】：国防科学技术大学
【学位级别】：博士
【学位授予年份】：2015
【分类号】：TN432

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