基于软硬件协同仿真的IP核验证平台的设计

发布时间：2018-05-13 10:37

本文选题：协同仿真 + IP核验证　；参考：《哈尔滨工业大学》2015年硕士论文

【摘要】：伴随着So C芯片设计规模的不断提升,验证成本的不断增加,软硬件协同仿真技术以及基于平台的So C验证思想已成为业界主流。同时,随着FPGA设计的逐渐完善,基于FPGA的协同仿真不仅具有高效性更具有真实性,在提升整体验证效果方面,该研究具有重要意义。本文基于协同仿真思想,采用千兆以太网作为通信媒介,结合Leon3 So C平台与Xilinx公司的So PC系统构建了一个新型的IP核验证平台。该平台主要分为PC端与FPGA端两部分,PC端作为整个验证平台的主体,包含了四个并行运行的进程——Leon3 So C进程、TCP服务器进程、验证功能进程以及拓展功能进程,进程间的数据通信采用文本文件以及共享内存两种方式,同步控制信号采用了Event模式进行通信;FPGA端主要分为硬件逻辑部分以及So PC软件部分,在硬件逻辑中包含待测IP核。两者之间的通信采用了TCP协议进行可靠传输,在PC端采用Winsock API,在So PC软件中使用lwip库。同时为了便于IP核验证的进行,本文提出了一种基于以太网的自定义数据帧,与TCP协议联合使用。在本文最后给出了基本功能验证、基本性能测试以及基于Leon3 So C平台的整体功能验证的具体结果。实验表明,该IP核验证平台基本功能与整体功能均可以正常运行,并且在待测IP核逻辑较为复杂时(如达到1024位乘法器或以上复杂度),在验证速度方面具有较大优势。
[Abstract]:With the increasing scale of so C chip design and the increasing cost of verification, hardware / software co-simulation technology and platform based so C verification idea have become the mainstream of the industry. At the same time, with the gradual improvement of FPGA design, the collaborative simulation based on FPGA not only has high efficiency and authenticity, but also plays an important role in improving the overall verification effect. In this paper, based on the cooperative simulation idea, a new IP core verification platform is constructed by using Gigabit Ethernet as the communication medium and combining the Leon3 so C platform with Xilinx's so PC system. The platform is divided into two parts: PC and FPGA as the main part of the whole verification platform, which includes four parallel running processes: Leon3 so C process, FPGA server process, verification function process and extended function process. The data communication between processes adopts two ways: text file and shared memory. The synchronous control signal uses Event mode to communicate. The FPGA end is mainly divided into hardware logic part and so PC software part, which includes IP core to be tested in the hardware logic. The communication between them adopts TCP protocol for reliable transmission, Winsock API for PC end and lwip library for so PC software. At the same time, in order to facilitate IP core verification, this paper proposes a custom data frame based on Ethernet, which is used in conjunction with TCP protocol. At the end of this paper, the results of basic function verification, basic performance test and the whole function verification based on Leon3 so C platform are given. Experiments show that both the basic function and the whole function of the IP core verification platform can run normally, and that the verification speed of the IP core verification platform can be greatly improved when the logic of the IP core under test is more complex (such as 1024 bit multiplier or more complexity).
【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN47

【参考文献】