神经形态芯片的关键模块和系统设计

发布时间：2018-05-13 11:53

本文选题：神经形态芯片 + 神经元电路　；参考：《浙江大学》2016年硕士论文

【摘要】：近几年来,深度学习算法快速发展,大规模的图像处理和迭代计算对硬件提出了新的要求。传统的计算机都是基于“冯诺依曼架构”设计,即数据在处理器和内存之间来回计算。这种架构适合数字运算和程序执行,但是并不适合处理图像、声音类信号。而人类的大脑却可以轻松地同步处理视觉、听觉和嗅觉等信号。通过研究人脑工作原理,学术界提出了一种不同于传统计算机架构的神经形态芯片,在处理图像和声音类信号方面有重大优势。为此,本文提出了一种模数混合超大规模脉冲型神经网络电路。本文先介绍了生物神经网络的原理和相应的电路模型,从理论上证明了神经网络电路设计的可行性,并根据应用的需求和电路自身的限制定义了芯片的内部结构。该芯片主要分为四个模块,神经元电路阵列、突触电路阵列、SRAM (Static Random Access Memory,静态随机存储器)存储单元阵列和AER (Address Event Representation)通信电路。其中,神经元电路阵列和突触电路阵列具有生物神经元和突触的时间特性,实现了脉冲频率可调,突触权重可配的功能。同时,通过改变突触电路和神经元电路的连接关系可以实现多种应用。利用AER电路,能够让芯片和微处理器通信,并通过更新SRAM单元中的突触权重值来研究不同种类的STDP (Spike-Timing Dependent Plasticity)学习算法的效果。该芯片采用了smic 180nm CMOS工艺,包含了总共32×32个SRAM单元,2×32个突触电路,32个IF神经元电路和AER通信电路。仿真结果显示,该芯片的输出和软件算法的输出完全相同,表明设计的芯片符合预期的要求。
[Abstract]:In recent years, deep learning algorithms have developed rapidly. Large scale image processing and iterative computing have put forward new requirements for hardware. Traditional computers are based on "Von Neumann architecture", that is, the data is calculated back and forth between the processor and the memory. This architecture is suitable for digital computing and program execution, but it is not suitable for processing graphs. Like, sound like signals. The human brain can easily synchronize the signals of vision, hearing and smell. By studying the working principle of the human brain, the academic community has proposed a neural morphologic chip different from the traditional computer architecture, which has a great advantage in the processing of images and sound signals. For this reason, a kind of ADM is proposed. In this paper, the principle of the neural network and the corresponding circuit model are introduced. The feasibility of the design of the neural network is proved theoretically, and the internal structure of the chip is defined according to the requirements of the application and the limitation of the circuit itself. The chip is divided into four modules, the neuron circuit is divided into two modules. Array, synapse circuit array, SRAM (Static Random Access Memory, static random memory) storage unit array and AER (Address Event Representation) communication circuit. In which, the neuron circuit array and the synaptic circuit array have the time characteristics of the biological neuron and synapse, realizing the pulse frequency adjustable, the synaptic weight can match work. At the same time, a variety of applications can be realized by changing the connection between the synaptic circuit and the neuron circuit. Using the AER circuit, the chip and the microprocessor can communicate, and the effect of the different kinds of STDP (Spike-Timing Dependent Plasticity) learning algorithm is studied by updating the synaptic weight value in the SRAM unit. The chip uses SMI The C 180nm CMOS process includes a total of 32 x 32 SRAM units, 2 x 32 synaptic circuits, 32 IF neuron circuits and AER communication circuits. The simulation results show that the output of the chip is exactly the same as the output of the software algorithm, indicating that the designed chip meets the expected requirements.

【学位授予单位】：浙江大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TN402

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