基于FPGA的高效脉冲压缩系统研究

发布时间：2018-05-14 23:08

本文选题：FPGA + 脉冲压缩　；参考：《中国航天科技集团公司第一研究院》2017年硕士论文

【摘要】：传统雷达信号处理机制将包括脉冲压缩处理在内的整套雷达成像算法放在DSP中完成,在处理点数多,数据量大的情况下DSP受限于其内存空间,难以独自完成整套成像算法,且其顺序执行指令的处理机制,也使得其进行大点数脉冲压缩处理的实时性较差。本文针对现代雷达系统工作模式多、处理数据量大的特点,提出一种基于FPGA处理平台,集信号采集、预处理和脉冲压缩于一身的高效脉冲压缩系统方案。首先,本文就信号采集基本原理与量化误差进行了阐述,明确了利用数字采样信号还原出原始模拟信号的条件,给出了理想情况下量化位数与信噪比的关系。随后给出A/D转换器的一些关键指标的计算方法和物理意义,为硬件测试提供了依据。对AD芯片EV10AQ190A的功能、结构和校正方法进行了详细阐述,对其关键性能指标进行了测试,其AD有效位数可达7.7位以上,无杂散动态范围为45dB以上。其次,本文对多相滤波结构的数学表达和物理构架进行了详细的推导与描述,体现了其在工程应用中的优越性。并基于理论分析将多相滤波结构运用于数字正交下变频的滤波抽取环节,优化了滤波器结构,有效地提高了处理效率。本文还结合了工程实例,对多相滤波结构的处理效果进行了软件仿真和硬件验证,结果证明基于多相滤波结构的预处理能够有效地实现防混叠、降速率和减少数据处理量的功能,且均能达到设计的预期效果和实用要求。再次,针对系统的核心功能,本文提出了一种基于复合FFT结构的频域脉冲压缩法。其FFT模块采用复式FFT结构,运算能力比基-4 Burst I/O结构提高了一倍;参考函数模块采用实时查表法,根据发射信号基本参数对参考信号进行实时生成。在Matlab和ISE平台上进行仿真,结果表明该方法能够高效地实现32768点脉冲压缩处理,处理点数多,实时性高,相同处理点数下其处理时间不到TMS320C6678型DSP耗时的一半,且处理结果满足工程应用要求。最后,本文将脉冲压缩模块封装成IP核,在以Virtex-7 FPGA为核心处理器的硬件平台上对整个高效脉冲压缩系统的性能进行验证。结果证明该系统能够高效实时的完成多模式脉冲压缩的功能,在脉冲压缩体制的小型化雷达处理机中有很大的应用价值。
[Abstract]:In the traditional radar signal processing mechanism, the whole radar imaging algorithm, including pulse compression processing, is put into DSP. In the case of large number of processing points and large amount of data, DSP is limited by its memory space, so it is difficult to complete the whole imaging algorithm alone. The processing mechanism of its sequential execution instruction also makes the processing of large number pulse compression worse in real time. In view of the characteristics of the modern radar system, which has many working modes and large amount of data, this paper presents an efficient pulse compression system based on FPGA processing platform, which integrates signal acquisition, preprocessing and pulse compression. Firstly, the basic principle of signal acquisition and quantization error are expounded, and the condition of reducing the original analog signal by using digital sampling signal is clarified, and the relationship between quantization bit number and SNR under ideal condition is given. Then the calculation method and physical meaning of some key indexes of the A / D converter are given, which provides the basis for the hardware test. The function, structure and correction method of AD chip EV10AQ190A are described in detail. The key performance indexes of AD chip are tested. The effective bit number of AD chip is more than 7.7 bits, and the range of no stray dynamic is more than 45dB. Secondly, the mathematical expression and physical framework of the polyphase filter structure are derived and described in detail, which reflects its superiority in engineering application. Based on the theoretical analysis, the polyphase filter structure is applied to the filtering and decimation of digital orthogonal down-conversion, the filter structure is optimized, and the processing efficiency is improved effectively. The software simulation and hardware verification of the multiphase filter structure are also carried out with an engineering example. The results show that the preprocessing based on the multiphase filter structure can effectively achieve anti-aliasing. The function of reducing the rate and reducing the data processing can reach the expected effect and practical requirement of the design. Thirdly, a frequency domain pulse compression method based on compound FFT structure is proposed for the core functions of the system. The FFT module uses the compound FFT structure, and its computing power is twice as high as that of the base -4 Burst I / O structure. The reference function module uses the real-time lookup table method to generate the reference signal in real time according to the basic parameters of the transmitted signal. The simulation results on Matlab and ISE platform show that the proposed method can efficiently realize 32768 point pulse compression processing, which has many points and high real-time performance. The processing time of the same processing points is less than half of that of TMS320C6678 DSP. The results meet the requirements of engineering application. Finally, the pulse compression module is encapsulated into IP core, and the performance of the high efficiency pulse compression system is verified on the hardware platform with Virtex-7 FPGA as the core processor. The results show that the system can efficiently and real-time complete the function of multi-mode pulse compression, and has great application value in the miniaturized radar processor of pulse compression system.
【学位授予单位】：中国航天科技集团公司第一研究院
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN791;TN957.51

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