纳米CMOS逻辑电路单粒子脉冲窄化效应研究

发布时间：2018-05-15 04:17

本文选题：单粒子效应 + 多位翻转　；参考：《深圳大学》2017年硕士论文

【摘要】：随着集成电路朝着更小的工艺尺寸,更高及集成度发展时,辐射环境中的粒子入射的影响越来越严重。因为粒子入射造成的单粒子效应已经成为航空航天电路失效的最重要原因之一。工艺尺寸的缩减使得节点之间的间距减小,导致在单粒子轰击发生时,节点之间的电荷共享越来越明显,由此引发的多位翻转使得一些传统的抗辐射设计如加大器件之间的间距,保护环等防护方法失效。基于电荷共享和多位翻转的基础上提出的脉冲窄化效应,是一种新型的防辐射设计思路。本文基于90纳米和65纳米CMOS双阱工艺,研究了90纳米工艺下基于脉冲窄化的抗辐射版图设计方法,65纳米工艺下基础逻辑电路的版图设计方法,65纳米工艺下复合逻辑电路的版图设计方法,65纳米工艺下抗辐射电路版图设计方法。以此总结出脉冲窄化在版图设计中的应用条件与准则。主要内容如下:(1)通过TCAD软件进行90纳米工艺和65纳米工艺的三维器件建模仿真。在90纳米工艺下,通过设置不同的器件间距和不同的入射粒子LET值的实验。解释在大的器件间距或者小的入射粒子LET值的情况下,输出节点出现的双峰电压现象。基于脉冲窄化的工作原理,提出或门PMOS版图部分适用脉冲窄化的冗余器件设计方法,与门的NMOS版图部分适用冗余设计方法,提出最小间距设计方法和高LET值器件不敏感的观点。(2)对比或门PMOS部分在90纳米和65纳米的粒子入射实验结果。提出随着器件工艺尺寸的缩减,或门的PMOS部分使用传统版图即可抵御单粒子脉冲无需冗余设计。对比与门NMOS部分在90纳米和65纳米的粒子入射实验结果,提出随着器件工艺尺寸的缩减,与门的NMOS部分使用冗余设计的效果会越来越好。(3)在65纳米工艺,进行复合逻辑电路的三维模型仿真实验。对比逻辑等效电路替换和复合逻辑电路的冗余设计两种方法,证明冗余设计方法在设计的简易度和稳定性上更为优秀。应用脉冲窄化的设计方法的建议:1.复杂的逻辑电路表达式应该通过逻辑等效尽量转换成与门,或门的组合2.观察版图结构,不管在PMOS还是NMOS区域,器件结构出现为串联结构,即可通过冗余设计进行来加强脉冲窄化,抵御单粒子脉冲。最后,本文对脉冲窄化在更小的工艺尺寸的应用和NMOS器件的防护设计的研究方向进行展望。
[Abstract]:With the development of integrated circuits towards smaller process size, higher integration, the impact of particle incidence in radiation environment is becoming more and more serious. The single particle effect caused by particle incidence has become one of the most important reasons for the failure of aerospace circuits. The reduction of process size reduces the distance between nodes, resulting in more and more charge sharing between nodes when single particle bombardment occurs. The multi-bit flip caused by this causes some traditional anti-radiation design methods, such as increasing the distance between devices, protection ring and so on, to invalidate the traditional anti-radiation design methods. The pulse narrowing effect based on charge sharing and multi-bit inversion is a new design idea of radiation protection. Based on 90 nm and 65 nm CMOS double well process, The layout Design method of basic Logic Circuits in 90 nm process based on Pulse narrowing the layout Design method of compound Logic Circuits under 65 nm process Radiation circuit layout design method. The application conditions and criteria of pulse narrowing in layout design are summarized. The main contents are as follows: 1) 3D device modeling and simulation of 90 nm process and 65 nm process are carried out by TCAD software. Under 90 nm process, different device spacing and LET value of incident particles were set. This paper explains the bimodal voltage phenomenon at the output node in the case of large device spacing or small incident particle LET value. Based on the working principle of pulse narrowing, this paper proposes a design method of redundant device which is suitable for pulse narrowing in PMOS layout, and redundancy design method in NMOS layout part of gate. A minimum spacing design method and an insensitive viewpoint of high LET value devices are proposed to compare the experimental results of the gate PMOS part at 90 nm and 65 nm particles. It is proposed that with the reduction of the process size of the device or the use of traditional layout in the PMOS part of the gate, the single particle pulse can be resisted without redundancy. Comparing with the experimental results of the gate NMOS part at 90 nm and 65 nm particle incidence, it is proposed that with the reduction of the device process size, the effect of using redundant design with the NMOS part of the gate will be better and better in the 65 nm process. The three-dimensional model simulation experiment of compound logic circuit is carried out. Comparing the two methods of logic equivalent circuit replacement and redundant design of compound logic circuit, it is proved that the redundancy design method is more excellent in design simplicity and stability. A proposal for applying the design method of pulse narrowing: 1. Complex logic circuit expressions should be converted as much as possible into gates, or combinations of gates, through logical equivalence. In the PMOS or NMOS region, the device structure appears in series structure, which can enhance the pulse narrowing by redundant design and resist the single particle pulse. Finally, the application of pulse narrowing in smaller process size and the research direction of NMOS device protection design are prospected.
【学位授予单位】：深圳大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN791

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