基于0.13umCMOS工艺的双通道UART芯片设计

发布时间：2018-05-17 14:07

本文选题：通用异步收发器 + 专用集成电路　；参考：《电子科技大学》2015年硕士论文

【摘要】：通用异步收发器,通常称为UART,采用串行数据总线,作为一种异步收发传输器,被用于异步系统之间的通信。该总线为双向通信,可以实现全双工数据传输。因其传输线少、传输距离远、可靠性高、成本低等优点,被广泛应用于计算机、工业控制等通信系统。新一代的计算机系统采用高端处理器,大大提升了数据处理速度,可以在短时间内处理大量任务。这些处理器的工作电压通常是3.3V、2.5V或者1.8V。因此,与CPU相连接的UART也必须随之改进设计,以进一步降低CPU的开销,提升整体系统的性能。而实现高性能的UART,必须将波特率、FIFO深度、供电电压、功耗等特性指标考虑在内。本文采用SMIC 0.13μm CMOS工艺,在3.3V PAD供电电压和1.2V Core供电电压下,基于低分辨率时钟预比例器结构,设计了一款波特率可达5 Mbps的双通道UART。采用低分辨率时钟预比例器结构,利用有理数分频来取代整数分频,可以很大程度上扩宽波特率的范围,提高UART性能和传输精度。同时,多通道设计可使多个通道同时收发数据,大大提高了数据传输速度。为了降低CPU的开销,本文为发送模块和接收模块各自设计了一个64字节大小的FIFO,在DMA操作的配合下可实现字符块传输。同时,本文设计了一种包含4级中断的中断模式,包括发送器中断、接收器中断、接收线状态中断、调制解调器中断等,大大降低了CPU的访问次数,使CPU可以处理更多的任务。为了便于调试,实现片内诊断功能,本文还设计了回写模式。此外,本文还为每个通道设计了14个内部寄存器,通过配置寄存器实现UART的不同模式,可通过地址线进行选择。为了降低系统的功耗,设计中采用门控时钟来降低时钟信号的翻转率,操作数分离使某一单元保持静态等策略来降低动态功耗。版图设计在SMIC1P6M工艺下完成。经验证,在系统时钟80MHz下波特率5Mbps,静态功耗为45.32mW,core版图面积为0.238mm2。本文与现有相似功能结构的芯片相比,在FIFO深度上有所增加,功耗和面积等指标方面大大减小。
[Abstract]:Universal asynchronous transceiver, commonly known as UART, uses serial data bus as an asynchronous transceiver for communication between asynchronous systems. The bus is two-way communication and can realize full duplex data transmission. It is widely used in computer, industrial control and other communication systems because of its advantages of less transmission lines, long transmission distance, high reliability and low cost. The new generation of computer systems use high-end processors, greatly improving the speed of data processing, can handle a large number of tasks in a short time. The operating voltages of these processors are typically 3.3 VV 2.5 V or 1.8 V. Therefore, the UART connected with CPU must be improved to further reduce the overhead of CPU and improve the performance of the whole system. In order to achieve high performance UART, the baud rate and FIFO depth, power supply voltage and power consumption must be taken into account. Using SMIC 0.13 渭 m CMOS process, a dual-channel UART with a baud rate of up to 5 Mbps is designed under 3.3 V PAD and 1.2 V Core power supply voltages, based on the low-resolution clock preratio structure. The low resolution clock preratio structure and rational frequency division instead of integer frequency division can greatly widen the range of baud rate and improve the performance and transmission accuracy of UART. At the same time, multi-channel design can make multiple channels send and receive data simultaneously, which greatly improves the speed of data transmission. In order to reduce the overhead of CPU, this paper designs a 64-byte FIFO for the sending module and the receiving module, which can realize the character block transmission with the cooperation of the DMA operation. At the same time, this paper designs an interrupt mode with four levels of interrupt, including transmitter interrupt, receive line state interrupt, modem interrupt, etc., which greatly reduces the number of CPU access and enables CPU to handle more tasks. In order to debug easily and realize the function of in-chip diagnosis, this paper also designs the write-back mode. In addition, 14 internal registers are designed for each channel. Different modes of UART are realized by configuration registers, which can be selected by address lines. In order to reduce the power consumption of the system, the gating clock is used to reduce the clock signal turnover rate, and the separation of operands to keep a unit static to reduce the dynamic power consumption. Layout design is completed under SMIC1P6M process. It is verified that under the system clock 80MHz, the baud rate is 5Mbpsand the static power consumption is 45.32mWN core. The layout area is 0.238mm ~ 2. Compared with the existing chips with similar functional structures, the depth of FIFO is increased, and the power consumption and area are greatly reduced.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN402

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