基于FPGA的视频实时采集系统关键技术研究

发布时间：2018-05-18 19:37

本文选题：FPGA + 视频　；参考：《北方民族大学》2017年硕士论文

【摘要】：随着科技的进步和社会的发展,视频实时采集系统得到了越来越多的应用。由于FPGA具有大容量的逻辑资源和极强的并行处理能力,因而FPGA特别适合作为视频实时采集系统的核心处理单元。而且得益于FPGA芯片具有可重复编程性,这就使得基于FPGA的视频实时采集系统相对于其它类型的视频实时采集系统来说,系统的维护和升级变得更为简单。当系统硬件需要少量改进时,可以在FPGA内部设计新的片内逻辑,而不用重新进行FPGA芯片外围电路的设计,这就在一定程度上节约了资源,减少了人力物力的损耗。本文主要对基于FPGA的视频实时采集系统进行了深入研究,将整个系统按照相应功能划分成五个模块,并将系统涉及的一些关键技术穿插在相应模块中进行设计。全局时钟模块,为系统的其他模块提供所需的时钟。摄像头配置模块,通过串行相机控制总线接口完成对OV7725 CMOS Sensor内部寄存器的配置,使得图像传感器能够输出预期配置的视频数据。摄像头视频流采集模块,用于实时采集摄像头产生的视频信号,并对采集到的视频信号进行同步化设计,最后通过采样和拼接,输出处理后的行场信号。SDRAM存储控制模块,通过对SDRAM存储器的控制,实现大容量视频图像数据的缓存,以及跨时钟域数据的交互。VGA显示控制模块,用于产生VGA显示器正常工作时需要的时序信号,实现实时视频图像的VGA显示驱动功能。系统的开发环境采用Quartus II 13.0,使用Verilog HDL语言完成对系统各模块的编写。通过Quartus II自带的仿真工具对系统的一些功能模块进行了仿真。系统的全局时钟模块,是通过Altera公司的FPGA中内嵌的锁相环进行设计的,通过Quartus II软件可以很方便地对锁相环进行设置,能够有效缩短开发时间。在SDRAM存储控制模块中使用了DCFIFO,解决了跨时钟域数据的交互问题。实验结果表明,系统能够正常工作,且采集到的视频画面比较清晰,能够实现视频实时采集的既定目标,具有一定的科研和应用价值。
[Abstract]:With the progress of science and technology and the development of society, video real-time acquisition system has been applied more and more. Because FPGA has large capacity of logic resources and strong parallel processing ability, FPGA is especially suitable as the core processing unit of video real-time acquisition system. Because of the repeatability of FPGA chip, the maintenance and upgrade of real-time video capture system based on FPGA is much simpler than that of other kinds of real-time video acquisition system. When the hardware of the system needs a little improvement, the new in-chip logic can be designed in FPGA, without redesigning the peripheral circuit of the FPGA chip, which saves the resources and reduces the loss of manpower and material resources to a certain extent. In this paper, the video real-time acquisition system based on FPGA is deeply studied, the whole system is divided into five modules according to the corresponding functions, and some key technologies involved in the system are interleaved in the corresponding modules to design. The global clock module provides the required clock for other modules of the system. The camera configuration module, through the serial camera control bus interface to complete the configuration of the OV7725 CMOS Sensor internal register, so that the image sensor can output the desired configuration of video data. The video stream acquisition module of the camera is used to collect the video signal generated by the camera in real time, and the synchronization design of the collected video signal is carried out. Finally, through sampling and splicing, the processed row field signal. SDRAM storage control module is output. Through the control of SDRAM memory, the cache of large capacity video image data is realized, and the interactive. VGA display control module of cross-clock domain data is used to generate the timing signals needed by the VGA display when it is working normally. Realize the real-time video image VGA display driver function. The development environment of the system is Quartus II 13.0, and Verilog HDL language is used to complete the writing of each module of the system. Some functional modules of the system are simulated by Quartus II simulation tools. The global clock module of the system is designed by the phase-locked loop embedded in the FPGA of Altera Company. The Quartus II software can set the PLL conveniently and shorten the development time effectively. DCFIFO is used in SDRAM storage control module to solve the problem of data interaction across clock domain. The experimental results show that the system can work normally, and the captured video picture is clear, and it can realize the fixed goal of real-time video acquisition, which has certain scientific research and application value.
【学位授予单位】：北方民族大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN791;TN948.6

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