用于植入式医疗设备的超低功耗SAR ADC设计

发布时间：2018-05-20 01:00

本文选题：植入式 + 模数转换器　；参考：《电子科技大学》2015年硕士论文

【摘要】：随着信息化技术的发展以及公民健康意识的增强,植入式医疗设备的研究成为热点。模数转换器(ADC)作为系统中关键的模块,要求其具有高精度、低功耗的性能。在众多ADC结构中,逐次逼近型(SAR)ADC由于其结构简单以及较高的能量利用效率,是实现该目标的较佳选择。本文基于55nm CMOS工艺,设计了一款工作在0.6V电源电压下,12位10kS/s的超低功耗SAR ADC。首先,为了降低比较器的功耗,本文通过分析传统vcm-based SAR ADC的逐次逼近过程中DAC输出电压差的变化规律,提出了电压窗口原理,针对不同幅度的DAC输出电压差采用不同精度的比较器进行比较判断。并在此基础上提出了应用了电压窗口技术的超低功耗SAR ADC结构。其次,在Matlab中对本文提出的超低功耗SAR ADC进行系统建模仿真,验证了结构的正确性。为了获得较优的系统性能,本文分析了超低功耗SAR ADC中一些非理想因素对系统性能的影响。主要包括电荷再分配型DAC中电容的失配以及噪声,前置放大器以及可再生锁存器的等效输入失调电压以及输入噪声,窗口电压的尺寸等。并将这些非理想因素引入到ADC系统模型中进行仿真,确定各个非理想因素的系统容忍范围,以此为参考指导各个模块的电路级设计。再次,本文针对SAR ADC中的各个模块进行了超低功耗设计。将电源电压降低到0.6V,并采用堆栈晶体管结构以及多阈值电压晶体管的方法有效降低了数字电路的功耗。但是低电源电压会降低采样开关的线性度,为此本文采用时钟倍压技术,提高采样开关的栅压来提高采样开关的线性度。最后,基于仿真工具Hspice对本文设计的超低功耗SAR ADC进行前仿真。仿真结果表明,在10kS/s的采样频率下,ADC的无杂散动态范围SFDR为83.9dB,信噪失真比SNDR为73.2dB,有效位数ENOB为11.87bits,功耗为287.3nW,FoM值为7.68fJ/Conv。窗口电压技术有效的降低了76.24%的比较器功耗,并因此降低了50.34%的系统总功耗。此外,本文基于55nm CMOS工艺完成了超低功耗SAR ADC版图的实现,并对ADC进行了后仿验证。后仿结果表明:在10kS/s的采样频率下,ADC的SFDR为77.8dB,SNDR为69.3dB,ENOB为11.22bits,功耗为624nW,FoM值为26.17fJ/Conv,达到了超低功耗的水平。最终完成的核心版图面积为435×210μm2。
[Abstract]:With the development of information technology and the enhancement of citizen's health consciousness, the research of implantable medical equipment has become a hot spot. As a key module in the system, A / D converter requires high accuracy and low power consumption. Among many ADC structures, successive approximation ADC is a better choice for achieving this goal because of its simple structure and high energy efficiency. Based on the 55nm CMOS process, an ultra-low power SAR ADC. which works at 0.6 V power supply voltage and 12 bits 10kS/s is designed in this paper. Firstly, in order to reduce the power consumption of the comparator, the principle of voltage window is put forward by analyzing the variation law of the output voltage difference of DAC in the process of successive approximation of traditional vcm-based SAR ADC. A comparator with different accuracy is used to compare and judge the output voltage difference of DAC with different amplitudes. Based on this, a very low power SAR ADC structure using voltage window technology is proposed. Secondly, the ultra-low power SAR ADC proposed in this paper is modeled and simulated in Matlab to verify the correctness of the structure. In order to obtain better system performance, the influence of some non-ideal factors in ultra-low power SAR ADC on system performance is analyzed. It mainly includes the capacitance mismatch and noise of charge redistribution type DAC, the equivalent input offset voltage of preamplifier and regenerative latch, the input noise, the size of window voltage and so on. These non-ideal factors are introduced into the ADC system model for simulation, and the tolerance range of each non-ideal factor is determined, which is used as a reference to guide the circuit level design of each module. Thirdly, the design of ultra-low power consumption for each module in SAR ADC is carried out in this paper. The power supply voltage is reduced to 0.6 V, and the stack transistor structure and multi-threshold voltage transistor are used to effectively reduce the power consumption of the digital circuit. But low power supply voltage will reduce the linearity of the sampling switch. In this paper, the clock voltage doubling technique is used to improve the linearity of the sampling switch by increasing the gate voltage of the sampling switch. Finally, the ultra-low power SAR ADC designed in this paper is pre-simulated based on the simulation tool Hspice. The simulation results show that the non-spurious dynamic range SFDR is 83.9 dB, the signal-to-noise distortion ratio (SNDR) is 73.2 dB, the effective bit number ENOB is 11.87 bits, and the power consumption is 287.3 nWN fom value of 7.68 fJ / Conv at the sampling frequency of 10kS/s. Window voltage technology can effectively reduce the power consumption of the comparator by 76.24% and thus the total power consumption of the system is reduced by 50.34%. In addition, the realization of ultra-low power SAR ADC layout based on 55nm CMOS process is completed, and the post-simulation verification of ADC is carried out. The post-simulation results show that the SFDR of 10kS/s is 77.8 dB / SNDR is 11.22 bits, and the power consumption is 624nW / F / Conv26.17fJ / Conv, which reaches the level of ultra-low power consumption. The final core area is 435 脳 210 渭 m2.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN792

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