应用于sEMG信号处理的低功耗ADC的设计

发布时间：2018-05-28 02:23

本文选题：逐次逼近型模数转换器 + 高速低功耗　；参考：《东南大学》2017年硕士论文

【摘要】：在表面肌电信号处理电路中大都需要模数转换器来将肌电信号这个模拟信号转换为数字信号,而应用的特殊领域需要模数转换器必须具有中等速度、中等精度和低功耗的特点,并且在CMOS工艺下较好实现。而逐次逼近型模数转换器(Successive Approximation Register Analog-to-Digital Converter,SAR ADC)具有由于具有中等的精度和中等的速度,采用CMOS工艺实现可保证较小的面积和功耗,在精度、速度、功耗和成本方面有着综合优势,因而被广泛的应用于医疗、无线传感网、数据存储等领域。本课题结合生物医疗应用领域的的要求,采用TSMC0.18μm CMOS工艺,设计了一款12bit 60MS/s低功耗SAR ADC。论文分别从构成SAR ADC的三个主要模块进行研究并改进SAR ADC。采用栅压自举开关、分段电容和单调开关切换方法提高DAC的线性度,减小电容的面积,降低功耗,采用局部共质心的版图布局提高匹配性;改进双尾电流动态比较器,提高电路的稳定性,降低了比较器的延时,降低了功耗和回踢噪声,对比较器进行了校准,将低失调电压。在逻辑控制上中使用到的D型触发器,选择真单向时钟(True Single Phase Clock,TSPC)的D型触发器,并进行改进,增加复位端口,简化了电路结构,降低电路动态功耗,提高电路的速度。本设计在Cadence环境下,对SAR ADC中关键模块和整体电路进行了电路前仿真和版图后仿真。版图总面积为550μm*175μm,电路后仿真的结果是:采样率为60MS/s时,SARADC的信号噪声失真比达到69dB,无杂散动态范围为67.4dB,有效位达到10.9bit,电路总功耗到达9.36mW,满足设计指标要求。
[Abstract]:In the surface EMG signal processing circuit, the analog-to-digital converter is required to convert the analog signal into digital signal, and the application of the special field requires that the ADC must have the characteristics of medium speed, medium accuracy and low power consumption. And it is well realized in CMOS process. The successive approximation analog-to-digital converter (ADC) has the advantages of low area and power consumption due to its moderate accuracy and medium speed, and has the advantages of precision, speed, power consumption and cost. Therefore, it is widely used in medical treatment, wireless sensor network, data storage and other fields. According to the requirements of biomedical application field, a low power 12bit 60MS/s SAR CMOS is designed by using TSMC0.18 渭 m CMOS process. In this paper, three main modules of SAR ADC are studied and improved. Using the gate voltage bootstrap switch, piecewise capacitance and monotone switch switching method to improve the linearity of DAC, reduce the area of capacitance, reduce power consumption, use the layout of local cocenter to improve matching, improve the dynamic comparator of double tail current, The stability of the circuit is improved, the delay of the comparator is reduced, the power consumption and backkick noise are reduced, and the comparator is calibrated to reduce the offset voltage. The D type flip-flop used in logic control, the true unidirectional clock true Single Phase lockTSPC type D flip-flop is selected and improved to increase the reset port, simplify the circuit structure, reduce the dynamic power consumption of the circuit and improve the speed of the circuit. In the Cadence environment, the key modules and the whole circuit in SAR ADC are simulated before and after layout. The total layout area is 550 渭 m ~ (175) 渭 m. The simulation results are as follows: when the sampling rate is 60MS/s, the signal noise distortion ratio is 69 dB, the non-spurious dynamic range is 67.4 dB, the effective bit is 10.9 bit, and the total power consumption of the circuit is 9.36 MW, which meets the design requirements.
【学位授予单位】：东南大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN792

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