12位100MSps低功耗SAR ADC的研究与设计

发布时间：2018-05-28 04:14

本文选题：高速低能耗 + 模数转换器　；参考：《电子科技大学》2017年硕士论文

【摘要】：为了适应无线通信、可穿戴设备、高速数字信号处理等领域的高速发展,作为模拟信号与数字信号接口桥梁的模数转换器(ADC)在高速、高精度、低能耗方向的研究将变得更加重要。由于高性能ADC在速度、精度、能耗之间相互限制,特别在工艺尺寸和电源电压缩减的情况下,器件的小尺寸效应更加突出,传统模拟域的高速ADC架构方案优势明显降低。为了充分发挥先进工艺线的优势及配合高速数字电路,本文在理论分析和建模验证的基础上,基于标准40nm工艺设计实现了一款12位100MSps、应用于超高速时间交织ADC中的单通道SAR ADC。首先,论文采用了非二进制电容阵列架构及较小的单位电容值,只需要将参考电平建立在冗余范围内即可,很大程度缩减了参考电平的建立时间,同时通过辅助DAC的补偿作用,将DAC建立的参考电平理论值置于冗余区间的中间,使得ADC能够同时容忍参考电平建立误差的正向和负向偏差,另外使用较小的DAC电容值可以减小建立时的动态功耗。其次,非二进制电容阵列存在冗余量可以容忍量化出错,ADC的高五位采用单级Latch锁存比较器量化,低八位采用预放大+Latch进行量化,两种不同精度比较器分时工作,可有效降低高位量化的功耗开销,在完成整个量化周期后将高精度比较器关闭,也可减小比较器的静态功耗,单级Latch对高位量化时,大信号输入不经过预放大级电路,减小比较器比较延时。最后,SAR逻辑电路采用新型锁存型结构,配合异步时序逻辑的使用,数据锁存及编码延时相比于传统的触发器逻辑延时大大减小,同时,本文还采用了比较器输出结果不经过锁存直接编码的技术,有效的减小了SAR逻辑单元中数据锁存的时间延时。基于标准40nm工艺完成电路和版图设计后,提取寄生参数并对电路进行了整体性能验证仿真。在100MS/s采样频率,输入信号接近奈奎斯特频率附近时,本次设计的SAR ADC的SFDR、SNDR、ENOB分别达到83.63d B、72.98dB、11.83bits,同时ADC的功耗开销为6.1m W,FoM值为16.8fJ/conv,芯片CORE电路面积为0.018mm~2。最后该单通道ADC应用于超高速时间交织ADC后在标准40nm CMOS工艺上进行流片验证,测试结果显示,DNL的最大最小值分别为1.08LSB和-0.864LSB;INL的最大最小值分别为3.76LSB和-0.48LSB,动态范围SFDR为:74.68dB,信噪失真比SNDR为:62.32dB,有效位数ENOB为:10.06Bit。
[Abstract]:In order to adapt to the rapid development of wireless communication, wearable devices, high-speed digital signal processing and other fields, ADCA / D converter, as an interface bridge between analog signal and digital signal, has high speed and high precision. Research on the direction of low energy consumption will become more important. Because high performance ADC is limited in speed, precision and energy consumption, especially in the case of process size and power supply voltage reduction, the small size effect of the device is more prominent, and the advantages of high-speed ADC architecture in traditional analog domain are obviously reduced. In order to give full play to the advantages of advanced process line and cooperate with high-speed digital circuit, based on theoretical analysis and modeling verification, a 12-bit 100MSps is implemented based on standard 40nm process design, which is applied to single-channel SAR ADC in ultra-high-speed time-interleaved ADC. First of all, the non-binary capacitor array architecture and small unit capacitance value are adopted in this paper. Only the reference level is set up in the redundant range, which greatly reduces the establishment time of the reference level. At the same time, the compensation function of DAC is assisted. The theoretical value of reference level established by DAC is placed in the middle of the redundant range, which enables ADC to tolerate both positive and negative deviation of reference level establishment error. In addition, the dynamic power consumption can be reduced by using smaller value of DAC capacitance. Secondly, the redundancy of non-binary capacitor array can tolerate quantization error. The high five bits are quantized by single stage Latch latch comparator, and the low eight bits are quantized by preamplifying Latch. The two kinds of comparators with different precision work in time sharing. It can effectively reduce the power cost of high quantization, turn off the high precision comparator after the whole quantization cycle, but also reduce the static power consumption of the comparator. When single stage Latch quantizes the high position, the large signal input does not go through the preamplifier stage circuit. Reduce comparator comparison delay. Finally, the SAR logic circuit adopts a new latch structure, and with the use of asynchronous sequential logic, the data latch and coding delay are greatly reduced compared with the traditional trigger logic delay, at the same time, This paper also adopts the technology that the output result of comparator is not directly encoded by latch, which effectively reduces the time delay of data latch in SAR logic unit. After circuit and layout design is completed based on standard 40nm process, parasitic parameters are extracted and the overall performance of the circuit is verified and simulated. When the sampling frequency of 100MS/s and the input signal are close to Nyquist frequency, the SNDRENOB of SAR ADC designed in this paper reaches 83.63dBU 72.98dBU 11.83 bits, meanwhile, the power consumption of ADC is 6.1m WN FoM is 16.8fJ / conv. and the area of chip CORE circuit is 0.018mm / m ~ (-2). Finally, the single-channel ADC is used to verify the flow sheet in the standard 40nm CMOS process after interleaving ADC at ultra-high speed. The results show that the maximum and minimum values of 1.08LSB and -0.864 LSB-INL are 3.76LSB and -0.48LSB. the dynamic range SFDR is 74.68dB, the signal-noise-distortion ratio (SNDR) is: 62.32dB, and the effective digit ENOB is 10.0: Bit06.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN792

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