多芯片电源配送网络分析与去耦设计

发布时间：2018-06-04 22:54

本文选题：多芯片电源配送网络 + 多输入阻抗　；参考：《西安电子科技大学》2015年硕士论文

【摘要】：随着电路板高速高密度的发展趋势,电路板实现的功能越来越多,不可避免的出现多个芯片负载共用同一个电源/地平面的情况,这时电源/地平面在不同的频率处表现出明显的全局特性和本地特性。在全局特性中,各个芯片电源端口之间相互影响,电源端口之间感受到的阻抗以及电源噪声相互叠加;本地特性中去耦电容为芯片提供高频电流,电源端口之间几乎没有相互影响。再加之IC工艺向更小尺寸发展,芯片电压逐渐降低、电流密度逐渐增大以及功耗的增加,使得电源噪声容限进一步降低。这些因素造成当今高速电源配送网络分析与设计变得越来越具有挑战性。传统的基于频域目标阻抗法适用于单个芯片负载情况,已不能够指导当今的高速电源分配网络设计,为能给电路板中每个高速数字芯片提供稳定供电电压,设计出针对多芯片的电源配送网络是非常有必要的。另外,去耦电容器在电路板的位置以及布局形式对其抑制噪声的能力有着明显的影响。对于单个去耦电容器来说,电容器的位置主要影响芯片与电容器之间的扩散电感,电容器越靠近芯片,这个电感越小。因此,在满足布局布线要求下,电容器应尽可能靠近数字芯片。对于多个电容来说,电容器布局方式对电源噪声抑制也会产生影响,针对目前比较常用的两种布局形式:环形布局与栅格形布局,通过相关的软件仿真发现,在相同的条件下,不论从端口整体阻抗曲线方面还是从电源噪声峰值方面,环形布局形式都要优于栅格形布局。本文详细分析了PDN各组成部分在整个系统PDN中所起的作用以及多芯片PDN设计方法,通过仿真对比多输入阻抗与单输入阻抗表征PDN的不同,说明了在多芯片PDN设计中多输入阻抗要比单端口自阻抗更合适。以此为基础,选用多输入阻抗指导多芯片PDN的设计。其中主要的设计思路如下,首先,从SI-wave中提取首要设计芯片处的多输入阻抗,利用矢量拟合得到该多输入阻抗的有理函数并导入到电容器选择软件中,得到针对该芯片的去耦方案设计,把选出的去耦电容器以合理的布局方式摆放在芯片电源端口周围,然后再以同样的方法得到其他芯片的去耦方案设计,直到每个芯片电源端口在规定频域内的阻抗曲线在目标阻抗曲线以下,这样完成了多芯片PDN设计。最后,把设计完成的PDN网络在时域中仿真验证来说明本设计方法的正确性。
[Abstract]:With the development trend of high speed and high density of circuit board, more and more functions of circuit board are realized, so it is inevitable that multiple chip loads share the same power supply / ground plane. At this time, the power / ground plane shows obvious global and local characteristics at different frequencies. In the global characteristic, each chip's power port affects each other, the impedance and noise of the power port are superimposed, and the decoupling capacitance provides the high frequency current for the chip. There is little interaction between power ports. In addition, with the development of IC technology to smaller size, the voltage of the chip decreases gradually, the current density increases and the power consumption increases, which further reduces the noise tolerance of the power supply. These factors make the analysis and design of high-speed power distribution network more and more challenging. The traditional impedance method based on frequency-domain target is suitable for the load of single chip. It can not guide the design of high-speed power distribution network and provide a stable power supply voltage for each high-speed digital chip in the circuit board. It is necessary to design a multi-chip power distribution network. In addition, the position and layout of decoupling capacitors in the circuit board have a significant impact on its ability to suppress noise. For a single decoupling capacitor, the position of the capacitor mainly affects the diffusion inductance between the chip and the capacitor. The closer the capacitor is to the chip, the smaller the inductance is. Therefore, the capacitor should be as close to the digital chip as possible under the requirement of layout and wiring. For multiple capacitors, the capacitor layout will also have an effect on the noise suppression of power supply. In view of the two commonly used layouts: ring layout and grid layout, it is found by software simulation that under the same conditions, The ring layout is superior to the grid layout in terms of the impedance curve of the port and the peak noise of the power supply. In this paper, the function of each component of PDN in the whole system PDN and the design method of multi-chip PDN are analyzed in detail. The differences between multi-input impedance and single-input impedance are compared by simulation. It is shown that the multi-input impedance is more suitable than the single-port self-impedance in the multi-chip PDN design. On this basis, multi-input impedance is selected to guide the design of multi-chip PDN. The main design ideas are as follows: firstly, the multi-input impedance of the primary design chip is extracted from SI-wave, the rational function of the multi-input impedance is obtained by vector fitting and imported into the capacitor selection software. The decoupling design for the chip is obtained. The selected decoupling capacitors are arranged around the power supply port of the chip in a reasonable layout, and then the decoupling scheme design of other chips is obtained by the same method. Until the impedance curve of each chip power port in the specified frequency domain is below the target impedance curve, the multi-chip PDN design is completed. Finally, the PDN network is simulated in time domain to illustrate the correctness of the design method.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN402

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