基于FPGA的多通道数字下变频系统

发布时间：2018-06-05 09:05

  本文选题：软件无线电 + 数字下变频　； 参考：《西华师范大学》2017年硕士论文

【摘要】：针对目前电子技术和通讯技术等领域内信号提取过程中存在的噪音与混叠的弊病,本课题改进了一种数字下变频系统,通过其在FPGA芯片上增加级数并降低阶数来增强系统抗混叠度的设计方式,不仅降低了设计的复杂程度、节约了设计成本及能耗,且由于FPGA硬件平台的可重构能力,使得数字下变频系统(DDC)实时更新灵活。本课题以信号的基本采样理论为基础,研究基于FPGA的多通道DDC设计方案。课题中针对过程中所运用信号处理基本算法、各部分实现方法进行深入分析。采用自上而下分析方法,详尽研究下变频系统当中重要组成部分,如数字控制振荡器(NCO)、混频器以及梳状滤波器组、半带滤波器以及有限冲激响应滤波器等重要构造。基于FPGA平台对系统中各个子系统分别进行调试与仿真,使用QuartusⅡ软件中VHDL语言编程与IP核宏模块的调用方式设计数控振荡器模块与混频器模块,运用Matlab中的FDAtool软件包与IP核结合方式设计多种滤波器组合模块,最终将各个子模块调用到Matlab软件中进行整体调试,验证设计目标。针对每个模块分别展开分析,NCO运用坐标旋转(CORDIC)算法实现,信号生成快、占用资源少;混频器模块运用乘法算法原理,简单、芯片引脚利用率降低;梳状滤波器组对原本单一的梳状滤波器(CIC)进行补充,运用延迟与移位语句降低对逻辑门的需求而有限冲激响应滤波器模块对信道中的信号进行整形,采用直线型与窗函数两种方法对比来选择最优处理方式。系统测试表明,该系统可以完整实现数字下变频的功能,能不失真地还原输入信号。NCO采用迭代相加方案,降低芯片引脚实际利用率;CIC组合滤波器增进阻带衰减与此同时使带内容差降低到0.5dB以内;运用窗函数形式设计FIR滤波器经Matlab测试能滤除混叠噪音、整形滤波,还原有效信号。整体测试效果满足设计要求,达到设计目标。
[Abstract]:In view of the disadvantages of noise and aliasing in the signal extraction process in the fields of electronic technology and communication technology, a digital downconversion system is improved in this paper. The design method of enhancing the anti-aliasing degree of the system by increasing the series and decreasing the order on the FPGA chip not only reduces the complexity of the design, but also saves the design cost and energy consumption, and because of the reconfigurable ability of the FPGA hardware platform. The DDC system is flexible to update in real time. Based on the basic sampling theory of signal, the design scheme of multi-channel DDC based on FPGA is studied in this paper. In this paper, the basic algorithm of signal processing used in the process is analyzed in detail. Using top-down analysis method, the important components of down-conversion system, such as digital controlled oscillator (DCO), mixer and comb filter bank, half-band filter and finite impulse response filter, are studied in detail. Each subsystem of the system is debugged and simulated based on FPGA platform. The NC oscillator module and mixer module are designed by using VHDL language programming in Quartus 鈪，

本文编号：1981447