用于高速接口的锁相环电路研究与设计

发布时间：2018-06-06 21:18

本文选题：锁相环 + 高速接口　；参考：《山东大学》2015年硕士论文

【摘要】：现今高速接口系统设计通常都需要时钟来使系统内的各模块电路实现同步运行和确定系统间的通信协议。锁相环电路作为现代高速接口系统中的重要模块之一,产生时钟来使系统内的各模块电路得以运行。本文基于CSMC0.18umCMOS工艺,面向高速接口中的HDMI2.0接口标准,设计了一款锁相环电路,输入参考时钟经过该锁相环电路后生成25 MHz～600MHz的八个等间距的时钟信号。本文研究了锁相环的基本概念和电荷泵锁相环的各组成模块的原理；使用Cadence软件设计了电荷泵锁相环各模块电路,包括鉴频鉴相器、电荷泵、环路滤波器、压控振荡器、分频器和LDO电路。设计鉴频鉴相器时考虑了死区问题,加入延时单元；采用了电流转向电荷泵,由两路互补的开关和单位增益运算放大器构成,可以改善电荷共享效应的影响；采用四级差分型的环形压控振荡器,以满足八个等间距的时钟信号的要求；设计了一个高速的TSPC型二分频电路和一个五分频电路级联的十分频器；因锁相环对电源波动十分敏感,设计了一款LDO专门用来为其他模块提供纯净和稳定的电源电压,将3.3V输入电源电压转换为1.8V稳定的输出电压。最后进行了仿真验证,结果表明该锁相环电路能实现预期的功能。本文设计的电荷泵锁相环电路以最新的HDMI2.0接口标准为依据,具有很好的应用价值和研究意义。
[Abstract]:Nowadays, the design of high speed interface system usually needs a clock to realize the synchronous operation of each module circuit in the system and to determine the communication protocol between the systems. As one of the most important modules in modern high speed interface system, PLL circuit generates clock to make each module circuit run. Based on CSMC 0.18um CMOS technology and HDMI 2.0 interface standard in high speed interface, a phase locked loop (PLL) circuit is designed in this paper. After the input reference clock is passed through the PLL circuit, eight equal spacing clock signals of 25 MHz are generated. In this paper, the basic concept of PLL and the principle of every module of CPPLL are studied, and the circuits of CPPLL are designed with Cadence software, including frequency discriminator, charge pump, loop filter, voltage-controlled oscillator, etc. Frequency divider and LDO circuit. In the design of the phase discriminator, the dead-time problem is considered, the delay unit is added, the current steering charge pump is adopted, which is composed of two complementary switches and the unit gain operational amplifier, which can improve the effect of charge sharing. A four-stage differential ring voltage-controlled oscillator is used to meet the requirements of eight equal spacing clock signals, and a high speed TSPC two-frequency divider and a five-frequency divider cascade are designed. Because PLL is very sensitive to power fluctuation, a LDO is designed to provide pure and stable power supply voltage for other modules. The 3.3V input power supply voltage is converted to 1.8V stable output voltage. Finally, the simulation results show that the PLL circuit can achieve the desired function. The charge-pump PLL circuit designed in this paper is based on the latest HDMI 2.0 interface standard and has good application value and research significance.
【学位授予单位】：山东大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN402

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