可延展柔性互连模型研究

发布时间：2018-06-09 07:03

本文选题：可延展 + 柔性　；参考：《西安电子科技大学》2015年硕士论文

【摘要】：随着集成电路技术的发展,集成电路的发展趋势一直遵循着摩尔定律不断进行发展,集成度不断增加,而特征尺寸不断减小,同时集成电路的性能也在不断的提高。随着集成电路集成度不断提高,特征尺寸在不断地减小,互连线对于延时,功耗的影响也在不断增加。尤其是在集成电路与半导体器件的特征尺寸进入纳米量级后,高频下由互连线的一些由于高频产生的效应导致的信号延迟增加、能耗不断升高和带宽也变窄等互连效应变得非常突出。互连线的一些相关特性俨然已经成为了当前阶段制约集成电路向前发展和半导体器件性能的主要因素。因此快速准确的提取高频集成电路的互连线寄生参数(电阻、电感、电容和电导)对于成功设计高性能的集成电路与半导体器件具有非常重要的研究意义。为了适应现如今人们对于电子产品的便携性,以及形状可变性等方面的越来越高的需求,半导体器件与电子材料的可延展柔性电子技术成为当下科研和学术界的焦点。可延展柔性无机集成电子器件指的是将电子器件建立在柔性可延展的基底上,这种可延展的柔性电子器件需要在保持传统无机脆性电子器件的比较高的性能与高可靠性的同时,还要具备一些可弯曲,可延展和可伸缩等柔性性能。随着可延展柔性电子技术的兴起,其互连结构与特性也成为研究热点与难点。针对可延展柔性无机集成电子器件与可延展柔性互连结构的特点,本文研究了高速集成电路的互连的各种相关模型,并在此基础上研究了一种互连可延展柔性电路的屈曲导线结构的互连寄生参数解析计算方法;建立屈曲导线互连寄生参数提取技术和集总参数电阻电感电容RLC模型。同时,为了能够让我们验证模型的正确性,我们利用HFSS软件对一种可延展互连结构进行了仿真,对比了通过仿真与计算两种方法得到的S参数。
[Abstract]:With the development of integrated circuit technology, the development trend of integrated circuit has been following Moore's law, the integration level is increasing, and the feature size is decreasing, at the same time, the performance of integrated circuit is also improving. With the increasing integration of integrated circuits, the feature size is decreasing, and the influence of interconnect on delay and power consumption is increasing. Especially when the characteristic size of integrated circuits and semiconductor devices reaches nanometer order of magnitude, the signal delay caused by some high-frequency effects of interconnects increases at high frequency. Interconnection effects, such as increasing energy consumption and narrowing bandwidth, have become very prominent. Some related characteristics of interconnects have become the main factors restricting the development of integrated circuits and the performance of semiconductor devices at the present stage. Therefore, fast and accurate extraction of the parasitic parameters (resistance, inductance, capacitance and conductance) of high frequency integrated circuits is very important for the successful design of high performance integrated circuits and semiconductor devices. In order to meet the increasing demand for the portability and shape variability of electronic products nowadays, the extensible flexible electronic technology of semiconductor devices and electronic materials has become the focus of current scientific research and academic circles. The extensible flexible inorganic integrated electronic device means that the electronic device is built on a flexible and extensible substrate. This extensible flexible electronic device needs to maintain the high performance and reliability of the traditional inorganic brittle electronic device. There are also some flexible properties, such as bending, extensibility and extensibility. With the development of extensible flexible electronic technology, its interconnection structure and characteristics have become a hot and difficult point. In view of the characteristics of extensible flexible inorganic integrated electronic devices and extensible flexible interconnection structures, various models of high-speed integrated circuit interconnection are studied in this paper. On the basis of this, an analytical calculation method of parasitic parameters of buckled wire structures with flexible interconnecting circuits is studied, and the technique of extracting parasitic parameters and the RLC model of lumped resistance inductance and capacitance are established. At the same time, in order to let us verify the correctness of the model, we use HFSS software to simulate an extensible interconnection structure, and compare the S parameters obtained by simulation and calculation.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN405.97

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