高效率CMOS包络跟踪技术的研究与设计

发布时间：2018-06-10 12:19

本文选题：CMOS工艺 + 包络跟踪技术　；参考：《电子科技大学》2017年硕士论文

【摘要】：随着通信技术的进一步发展,无线通讯设备将会越来越复杂,高效率的使用能源不仅能够延长电池的使用寿命,而且也会大大减少电子仪器的散热,提高仪器的可靠性。目前,包络跟踪技术由于其电路结构简单,易于集成以及提高系统效率效果明显等特点成为国内外研究的热点,本文对包络跟踪技术进行了详细的研究,并给出了数种提高效率的新结构,这些结构对于提高电路系统的效率具有非常重要的意义。首先,几种常见的包络放大器结构被一一简介,并分别对比了它们的优点和缺点,以便后文选择结构。紧接着是包络放大器的功耗分析,在这一部分,我们对包络放大器的每一个部分分别进行了分析,为后面提高效率的方法提供思路。本文首先采用了经典的包络放大器结构来设计一款基于0.18μm工艺的芯片,其中线性级由一个两级放大器构成,主要用来提供高频电流以及消除来自于开关的纹波电流;开关级由一个降压型DC-DC变换器和一些控制电路以及一个片外的电感构成,提供低频电流(占总电流比重很大),以此来提高效率。最终版图面积0.8mm×0.5mm。在电源电压3.3V,10MHz LTE信号,负载8欧姆情况下,最终输出功率为27dBm,整体效率为74%。然而,包络放大器的效率还有较大的提高空间,接着本文重点关注提高效率的方法并提出了三种提高效率的方法。在第一种方法中,利用一个轨到轨放大器来放大差异,使控制电路变得更加“准时”,这样开关打开和关断变得更及时,效率也因此提高了2个百分点(76%),版图面积却没有因此增加。在第二种方法中,我们发现当线性级的输出级放大器的NMOS管的栅压大于一个阈值电压时,线性级开始吸收纹波电流,我们将这些纹波电流用一个电容存储起来,最终将效率提高了2.3个百分点(76.3%)。在第三种方法中,提出了一种更激进的方法,当功率放大器输出功率低于一定值时,线性级和开关级停止工作,由一个直流电流提供电流,当输出功率较大时,所有电路模块都参与工作。这种方法有可能极大地提高整个系统的效率,最终初步仿真效率超过了87%。
[Abstract]:With the further development of communication technology, wireless communication equipment will become more and more complex. The efficient use of energy can not only prolong the service life of batteries, but also greatly reduce the heat dissipation of electronic instruments and improve their reliability. At present, envelope tracking technology has become a hot research topic at home and abroad because of its simple circuit structure, easy integration and obvious effect of improving the efficiency of the system. In this paper, the envelope tracking technology is studied in detail. Several new structures for improving efficiency are given, which are of great significance for improving the efficiency of circuit systems. Firstly, several common envelop amplifier structures are introduced, and their advantages and disadvantages are compared. Then there is the analysis of the power consumption of the envelope amplifier. In this part, we analyze each part of the envelope amplifier separately, and provide some ideas for improving the efficiency of the envelope amplifier. In this paper, a novel chip based on 0.18 渭 m process is designed with classical envelope amplifier structure. The linear stage is composed of a two-stage amplifier, which is mainly used to provide high frequency current and eliminate ripple current from switch. The switching level consists of a step-down DC-DC converter, some control circuits and an off-chip inductor, which provides a low frequency current (a large proportion of the total current) to improve efficiency. The final layout area is 0.8mm 脳 0.5mm. The output power is 27dBm and the overall efficiency is 74 under the condition of power supply voltage of 3.3V / 10MHz LTE and load of 8 ohms. However, there is still much room for improvement in the efficiency of the envelop amplifier. Then, this paper focuses on the methods of improving the efficiency and proposes three methods to improve the efficiency. In the first method, a rail to rail amplifier is used to amplify the difference, making the control circuit more "punctual," so that the switch on and off becomes more timely. Efficiency has thus increased by 2 percentage points, but the size of the territory has not increased as a result. In the second method, we find that when the gate voltage of the output stage amplifier of the linear stage is greater than a threshold voltage, the linear stage begins to absorb the ripple current, and we store the ripple current with a capacitor. In the end, the efficiency was raised by 2.3 percentage points or 76.3%. In the third method, a more radical method is proposed. When the output power of the power amplifier is below a certain value, the linear and switching levels stop working, and the current is supplied by a DC current, and when the output power is high, All circuit modules work. This method can greatly improve the efficiency of the whole system, and the initial simulation efficiency exceeds 87%.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN722

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