基于a-IGZO TFTs的低功耗D触发器设计

发布时间：2018-06-12 03:55

  本文选题：薄膜晶体管 + D触发器　； 参考：《华南理工大学学报(自然科学版)》2017年03期

【摘要】：设计了一个基于Pseudo-CMOS逻辑门的低功耗异步复位D触发器电路.该D触发器全部由n型a-IGZO TFTs(薄膜晶体管)构成,采用动态负载替代Pseudo-CMOS拓扑中的二极管连接负载,通过减少电路导通的概率来降低静态功耗.电路的输出级为锁存器,通过反馈通路减少由动态负载造成的输出摆幅降低对延迟的影响.将该D触发器应用于环行移位寄存器的设计中,结果表明,该触发器电路可有效降低或非门逻辑电路中的静态功耗.
[Abstract]:A low power asynchronous reset D flip-flop circuit based on Pseudo-CMOS logic gate is designed. The D-flip-flop consists of n-type a-IGZO TFTs (thin film transistor). The dynamic load is used to replace the diode connection load in Pseudo-CMOS topology, and the static power consumption is reduced by reducing the probability of circuit turn-on. The output stage of the circuit is a latch, and the effect of the output swing reduction caused by the dynamic load on the delay is reduced by the feedback path. The D flip-flop is applied to the design of the cyclic shift register. The results show that the flip-flop circuit can effectively reduce the static power consumption in the non-gate logic circuit.
【作者单位】： 华南理工大学电子与信息学院;
【基金】：国家自然科学基金资助项目(61274085) 广东省科技计划项目(2015B090909001)~~
【分类号】：TN783
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本文编号：2008225