短距离无线数传基带芯片后端设计

发布时间：2018-06-13 20:03

本文选题：逻辑综合 + 低功耗　；参考：《西安电子科技大学》2015年硕士论文

【摘要】：随着数字集成电路产业的迅猛发展,集成电路后端设计质量逐渐成为制约芯片良品率和生产成本的重要因素;随着集成电路工艺尺寸的不断缩小,集成电路芯片的应用领域不断扩大,目前在智能电子、可穿戴设备和医学上都有很广泛的应用。这些领域的应用使得数字IC芯片不断向低功耗的方向发展。在保证芯片性能的情况下,如何将功耗降至最低逐渐成为当前集成电路设计的重点。在无线数字通信技术大发展的背景下,短距离无线数传技术由于具有功耗低、面积小、成本低及实现简单等优点,已经在社会生活的方方面面都得到了应用。本文根据课题组的科研项目,完成了一款基于短距离无线数传的基带芯片的后端设计,介绍了芯片后端实现的具体过程,并对在后端实现过程中遇到的问题以及笔者对后端流程的理解进行了详细的说明和深入的分析。本文着重进行了以下几个方面的工作:(1)介绍了逻辑综合原理和逻辑综合过程,并详细介绍了综合阶段的低功耗设计方法——门控时钟综合技术。应用门控时钟综合技术对短距离无线数传基带芯片进行综合,将综合后的功耗从52m W降低至38mW,功耗降低了27%。(2)总结了电路设计的时序要求,对静态时序分析(STA)原理进行了详细介绍,简单说明了STA所用的工具以及STA工具的使用方法。并给出了存在违例的路径的人工处理方法,成功的修正了后端工具分析中出现的时序违例问题。(3)对后端设计流程和版图设计工具进行了介绍,并使用Astro完成了短距离无线数传基带芯片的版图设计,包括芯片面积、电源的规划、时钟树综合、布局工作和布线工作,并简单介绍了工艺天线效应产生的原因及解决方法,修正了版图设计时出现的工艺天线效应。对版图设计后的网表和寄生参数文件进行静态时序分析,发现问题并修改网表,然后再修改的网表基础上用ECO方法修正了版图。最终版图面积为1.87mm×2.39mm。(4)简单介绍了形式验证原理、版图的物理设计要求。对短距离无线数传基带芯片的最终版图网表与RTL级网表做了形式验证;采用Calibre对最终的版图做了DRC和LVS,以确保流片的质量。(5)完成了流片后的裸片封装工作,并对芯片进行了功能测试,最终芯片满足了设计要求。本文围绕上述工作,对集成电路后端设计过程中的原理性知识、工具的运用和实际的操作方法等方面进行了全面的介绍。
[Abstract]:With the rapid development of the digital integrated circuit industry, the design quality of the back end of the integrated circuit has gradually become an important factor that restricts the rate of good products and the production cost of the chip, and with the continuous reduction of the process size of the integrated circuit, IC chips are widely used in smart electronics, wearable devices and medicine. The applications of these fields make the digital IC chip develop to the direction of low power consumption. In order to ensure the performance of the chip, how to minimize the power consumption has gradually become the focus of the current IC design. With the rapid development of wireless digital communication technology, short-range wireless data transmission technology has been applied in all aspects of social life because of its advantages of low power consumption, small area, low cost and simple implementation. In this paper, according to the research project of the research group, a backend design of the baseband chip based on short-range wireless data transmission is completed, and the process of realizing the back-end of the chip is introduced. The problems encountered in the process of back-end implementation and the author's understanding of back-end flow are explained and analyzed in detail. This paper focuses on the following aspects: 1) introduces the principle of logic synthesis and the process of logic synthesis, and introduces in detail the low power consumption design method-gating clock synthesis technology in the synthesis stage. By using the gating clock synthesis technology to synthesize the short distance wireless digital baseband chip, the power consumption is reduced from 52m W to 38 MW, and the power consumption is reduced by 27%.) the timing requirements of the circuit design are summarized. The principle of static time sequence analysis (STAA) is introduced in detail. The tools used in STA and the usage method of STA tools are briefly described. The manual processing method of the illegal path is given, and the time sequence violation problem in the analysis of back-end tools is corrected successfully.) the back-end design flow and layout design tools are introduced. The layout design of short-range wireless digital baseband chip is completed by using Astro, including chip area, power source planning, clock tree synthesis, layout work and wiring work. Fixed the effect of craft antenna in layout design. The static time sequence analysis of the net table and parasitic parameter file after layout design is carried out, the problem is found and the net table is modified, and then the layout is corrected by eco method on the basis of the modified net table. The final layout area is 1.87mm 脳 2.39 mm. 4) the principle of formal verification and the physical design requirements of layout are briefly introduced. The final layout table and RTL level network table of short range wireless digital baseband chip are formally verified, and the final layout is made by calibre to ensure the quality of streaming chip. Finally, the chip meets the design requirements. In this paper, the principle knowledge, the application of tools and the practical operation methods in the design process of integrated circuit back-end are introduced in detail.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN402

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