混频多功能芯片的设计与实现

发布时间：2018-06-13 22:25

本文选题：混频多功能芯片 + 放大器　；参考：《西安电子科技大学》2015年硕士论文

【摘要】：在数字电路被芯片化、集成化改进的日渐成熟的同时,射频电路也向着小型化、芯片化的方向不断地发展,逐渐由无线收发(T/R)组件向着单片微波集成电路(MMIC)技术逐渐演变,芯片的整体尺寸日趋缩小,性能却在此过程中不断突飞猛进,这种转变带来的不仅仅是系统尺寸由组件向芯片的稳步过渡,更是整体功能由分立元件向混合信号系统的不断飞跃,对于人类技术的发展与革新起到日益重要的作用。构成T/R模块的众多分立元件当中,功率放大器与混频器是影响T/R模块的核心零部件,直接影响T/R模块的灵敏度和最低信噪比,其性能指标日益变为现有雷达系统的关键,反映了一个国家雷达技术的发展水平。对相控阵雷达系统中MMIC的仿真设计与测试方法进行了详细的研究,设计芯片主体为C波段(4-8GHz)无源双平衡混频器,其本振端口集成具有20dB增益的驱动放大器,射频端口集成增益为16dB的双向放大器,多功能芯片可同时实现上变频及下变频的使用要求。在对射频电路设计的基本理论做过细致研究之后,采用ADS软件首先对各分立元件进行原理图以及版图仿真设计,不断调整各部分的参数以优化性能指标,在确定性能满足要求之后对芯片中各组成部分进行集成以完成混频多功能芯片的仿真设计,系统仿真结果变频增益大于8dB且具有较好的频带内平坦度,端口回波损耗优于-10dB,端口间隔离度特性良好,满足设计前设定的指标要求,符合实际工程使用中的要求。设计版图采用中电集团13所ED 0.25μm PHEMT工艺线完成设计电路的流片处理,对晶圆片使用Cascade公司生产的探针台以及安捷伦公司的四端口矢量网络分析仪做晶圆片的裸片探针测试。对比测试结果与仿真结果并对整体结果进行详细记录与分析,对性能指标进行一定的研究,除个别性能指标出现稍许偏离仿真结果外,芯片整体性能满足使用要求及设计预期,能够达到工程应用的通用设计标准及产品级芯片的性能要求,继而对芯片尺寸做压缩处理以满足实际封装使用时面临的尺寸要求,对改版后的芯片再次流片并测试。测试结果表明芯片性能指标在芯片尺寸压缩后出现一定恶化,但仍处于实际使用中可以接受的范围内,芯片变频增益大于10dB,各端口回波损耗特性优于-5dB,各端口隔离度特性良好,设计目标基本与设计前所做方案设计基本一致,能够满足实际工程应用对于芯片的性能指标要求。
[Abstract]:While the digital circuits are becoming more and more integrated and improved, the RF circuits are becoming smaller and more integrated, and the wireless transceiver / transceiver T / R components are gradually evolving to the monolithic microwave integrated circuits (MMICs) technology. The overall size of the chip is getting smaller and smaller, but the performance of the chip in the process of rapid progress, this change does not only bring about a steady transition of system size from components to chips, It is also the continuous leap from discrete components to mixed signal systems, which plays an increasingly important role in the development and innovation of human technology. Among the many discrete components that make up the T / R module, power amplifiers and mixers are the core components that affect the T / R module, which directly affects the sensitivity and the lowest signal-to-noise ratio of the T / R module. Its performance index is increasingly becoming the key of the existing radar system. It reflects the development level of radar technology in a country. The simulation design and test method of MMIC in phased array radar system are studied in detail. The main chip is C-band 4-8GHz) passive dual-balanced mixer, and its local oscillator port integrated drive amplifier with 20dB gain. With a bidirectional amplifier with a gain of 16dB, the multi-function chip can meet the requirements of up-conversion and down-conversion at the same time. After the detailed research on the basic theory of RF circuit design, the principle diagram and layout simulation design of each discrete element is carried out by ads software, and the parameters of each part are adjusted to optimize the performance index. After the determinism can meet the requirements, the components of the chip are integrated to complete the simulation design of the mixed-frequency multifunctional chip. The simulation results show that the frequency conversion gain is more than 8dB and the system has a good in-band flatness. The return loss of the port is better than -10 dB, and the isolation between ports is good, which meets the requirements set before the design and meets the requirements of practical engineering. The design layout uses 13 Ed 0.25 渭 m pHEMT process lines of CLP Group to complete the wafer processing of the designed circuit. The wafers are tested by using Cascade's probe platform and Agilent's four-port vector network analyzer. Comparing the test result with the simulation result and recording and analyzing the whole result in detail, the performance index is studied to a certain extent. Except for some performance indexes deviating slightly from the simulation result, the overall performance of the chip meets the requirement of use and the design expectation. It can meet the general design standards of engineering applications and the performance requirements of product level chips. Then the chip size is compressed to meet the size requirements of actual packaging. The modified chip is reflow and tested. The test results show that the chip performance has deteriorated after chip size compression, but it is still in the acceptable range in practical use. The frequency conversion gain of the chip is greater than 10dB, the echo loss characteristics of each port is better than -5dB, and the isolation of each port is good. The design goal is basically the same as the scheme design before the design, and it can meet the requirements of the chip performance in practical engineering applications.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN402

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