基于UVM可重用验证平台的研究

发布时间：2018-06-17 00:05

本文选题：System + Verilog　；参考：《西安电子科技大学》2015年硕士论文

【摘要】：随着集成电路工艺与设计能力的不断发展,SoC设计规模与复杂度持续增加。这使得SoC验证工作的难度也日益增长,SoC的验证工作已成为集成电路设计过程中的严峻挑战。本论文针对验证开展研究,在研究分析System Verilog验证语言和通用验证方法学(UVM)的基础上,对SoC/IP的验证特征与验证需求进行分析,根据SoC中IP模块的相关协议规格搭建了验证平台,编写了通用验证组件。并根据验证方法、通用验证组件讨论了如何将验证平台重用于其他IP模块和系统级模块等核心问题。在设计验证阶段,首先分析了SoC体系结构,提出验证需求。利用UVM搭建验证平台。对于验证平台的结构,采用总线接口模型与抽象层次化结构相结合的形式,为下一步SoC/IP验证平台的设计实现打下基础。为保证验证平台具有可重用性的验证需求,文中选取APB、UART总线接口模型作为通用组件,设计顶层控制模块环境嵌套APB与UART通用组件子环境。在低层次组件中加入随机约束、事务项、phase机制,实现验证的随机性、可控性。在验证实施阶段,根据UART设计模块,分解覆盖点采用随机事务级激励编写测试项,在仅通过一条测试项的情况下,代码覆盖率与功能覆盖率分别达到99.60%与100%,以此说明该验证平台有效提高了测试效率。仿真结束后自动生成执行报告,记录验证环境运行的验证组件、寄存器配置信息,并通过UVM_INFO标示transaction传输时正确与错误的信息。在探究验证平台可重用性阶段,选取SPI待测模块,运用相同的验证平台。通过顶层控制模块选取自定义的UART、APB验证通用组件,从而配置生成适用于SPI的验证环境,通过执行测试项进行仿真工作,收集代码覆盖率100%。以此说明对模块级该验证平台的可重用性。再次选取APB子系统,通过结构图阐述该验证平台进行APB子系统级验证所需通用组件的结构与环境划分。以此证明基于UVM可重用验证平台,对传统验证平台在随机性、可复用性、自动化等方面进行了优化,对集成化SoC验证具有可行性。
[Abstract]:With the continuous development of IC technology and design capability, SoC design scale and complexity continue to increase. This makes the verification of SoC more and more difficult. The verification of SoC has become a severe challenge in the process of IC design. Based on the analysis of system Verilog verification language and universal verification methodology (UVM), the verification features and verification requirements of SoC / IP are analyzed, and the verification platform is built according to the protocol specifications of IP modules in SoC. A general verification component is written. According to the verification method, the common verification component discusses how to reapply the verification platform to other IP modules and system-level modules. In the phase of design and verification, the SoC architecture is analyzed and the verification requirements are put forward. UVM is used to build the verification platform. For the structure of the verification platform, the bus interface model and the abstract hierarchical structure are adopted to lay the foundation for the design and implementation of the next SoC / IP verification platform. In order to ensure the reusability of the verification platform, the API UART bus interface model is selected as the universal component, and the top-level control module environment is designed to nest APB and UART general component subenvironment. The randomness and controllability of verification are realized by adding random constraints and transaction item phase mechanism to the low level components. In the verification implementation phase, according to the UART design module, the decomposition coverage point uses random transaction-level incentives to write test items, and when only one test item is passed, The code coverage and function coverage are 99.60% and 100% respectively. At the end of the simulation, the execution report is generated automatically, the verification components running in the verification environment are recorded, the information of register configuration is recorded, and the correct and wrong information of transaction transmission is indicated by the transaction stack info. In the stage of exploring the reusability of verification platform, the SPI module is selected and the same verification platform is used. The self-defined UART APB is selected by the top-level control module to verify the universal components, so that the verification environment suitable for SPI is configured, the test items are executed to simulate, and the code coverage is 100%. This illustrates the reusability of the verification platform at the module level. The structure and environment partition of the general components needed for APB subsystem verification are illustrated by the structure diagram of APB subsystem. It is proved that based on UVM reusable verification platform, the traditional verification platform is optimized in randomness, reusability, automation and so on, which is feasible for integrated SoC verification.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN402

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