超薄SiGe虚拟衬底的制备与建模
发布时间:2018-06-17 10:38
本文选题:MOSFET + 应变硅 ; 参考:《电子科技大学》2015年硕士论文
【摘要】:在Moore定律的推动下,晶体管尺寸逐渐缩小,集成电路集成度越来越高,当特征尺寸进入到纳米量级,晶体管性能会受到小尺寸效应的影响。包括SiGe材料在内的应变Si技术,以其诸多优点成为现阶段保持Moore定律、同时提升器件性能的新材料技术。SiGe虚拟衬底主要是通过SiGe与Si材料间的晶格失配在沟道中引入应变。因而要实现性能优良的应变Si/SiGe器件需要制备出高质量的弛豫SiGe薄膜。良好的SiGe虚拟衬底要有高弛豫度、低缺陷密度、低表面粗糙度以及较薄的厚度,但这几项指标之间互有影响甚至互相对立。为了获得高质量且薄的SiGe虚拟衬底,本论文通过对SiGe合金材料应变弛豫机理的研究,设计出制备超薄SiGe虚拟衬底的方案并成功制备,并针对离子注入致超薄SiGe虚拟衬底应变弛豫的过程构建模型。本论文从SiGe和Si的晶格失配入手,阐明了SiGe中应变产生的原因;通过分析SiGe中应变弛豫与SiGe/Si界面处失配位错的关系,解释了SiGe外延薄膜应变弛豫的机理,给出了常见的临界厚度模型。本论文在研究位错与应变弛豫关系的基础上,结合SiGe合金的制备技术及常见的虚拟衬底的实现方法,设计出两种超薄SiGe虚拟衬底制备方案,经对比选择后采用Ar+离子注入的方案。针对此方案设计实验条件并成功制备出厚度仅为200nm的超薄SiGe虚拟衬底;同时研究了虚拟衬底的测试表征技术,对制备成功的超薄虚拟衬底进行测试、计算及分析,结果表明虚拟衬底的Ge含量为19.93%,弛豫度高达81.51%。本论文针对离子注入致超薄SiGe虚拟衬底应变弛豫的过程进行了建模。针对弹性多层薄膜系统,本文在已有的热应力失配模型的基础上,建立了由晶格失配引起的多层薄膜系统的应变分布物理模型,并推导出了其解析表达式;并进一步考虑到离子注入所导致的空位缺陷,将其纳入到多层薄膜系统的应变分布模型中,给出了离子注入所致的空位缺陷密度与弛豫度之间的解析关系式;将此模型应用的Si/SiGe双层系统构成的虚拟衬底中,得到了与实验数据较好的吻合。另外,本章探讨了Ar+离子注入后在材料中的分布对SiGe中杨氏模量的影响,由此出发构建了数值模型。
[Abstract]:Driven by Moore's law, the size of transistors shrinks and the integration of integrated circuits becomes more and more high. When the characteristic size reaches the nanometer level, the performance of transistors will be affected by the small size effect. Strained Si technology, including SiGe materials, has become the Moore's law at present because of its many advantages. At the same time, the new material technology. SiGe virtual substrate is introduced strain into the channel by lattice mismatch between SiGe and Si material. Therefore, it is necessary to fabricate high quality relaxation SiGe thin films in order to achieve high performance strained Si / SiGe devices. A good SiGe virtual substrate should have high relaxation, low defect density, low surface roughness and thin thickness. In order to obtain high quality and thin SiGe virtual substrate, in this paper, the strain relaxation mechanism of SiGe alloy material is studied, and the scheme of fabricating ultra-thin SiGe virtual substrate is designed and successfully prepared. A model for strain relaxation of ultra-thin SiGe virtual substrate induced by ion implantation was established. Starting with the lattice mismatch of SiGe and Si, the causes of strain generation in SiGe are explained, and the mechanism of strain relaxation in SiGe epitaxial film is explained by analyzing the relationship between strain relaxation in SiGe and mismatch dislocation at SiGe / Si interface. The common critical thickness model is given. Based on the study of the relationship between dislocation and strain relaxation, two kinds of ultra-thin SiGe virtual substrates are designed by combining the fabrication technology of SiGe alloy and the realization of common virtual substrates. Ar ion implantation was used after comparison and selection. According to this scheme, the experimental conditions were designed and the ultra-thin SiGe virtual substrates with thickness of only 200nm were successfully fabricated, and the testing and characterization technology of the virtual substrates was studied, and the ultra-thin virtual substrates were tested, calculated and analyzed. The results show that the GE content of the virtual substrate is 19.93 and the relaxation degree is up to 81.51. In this paper, the strain relaxation process of ultra-thin SiGe substrates induced by ion implantation is modeled. Based on the existing thermal stress mismatch model, the strain distribution physical model of the multilayer thin film system caused by lattice mismatch is established, and its analytical expression is derived. Furthermore, considering the vacancy defect caused by ion implantation, it is incorporated into the strain distribution model of multilayer thin film system, and the analytical relationship between the vacancy defect density and the relaxation degree caused by ion implantation is given. In the virtual substrate constructed by the Si-SiGe bilayer system which is applied to this model, the experimental data are in good agreement with each other. In addition, the effect of ar ion implantation on Young's modulus in SiGe is discussed, and a numerical model is constructed.
【学位授予单位】:电子科技大学
【学位级别】:硕士
【学位授予年份】:2015
【分类号】:TN304.2
【参考文献】
相关期刊论文 前1条
1 梅丁蕾,杨谟华,李竞春,于奇,张静,徐婉静,谭开洲;应用400℃低温Si技术制备应变Si沟道pMOSFET(英文)[J];半导体学报;2004年10期
,本文编号:2030748
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