基于CMOS工艺的一种逐次逼近型模数转换器的设计

发布时间：2018-06-19 00:49

本文选题：模数转换器 + 逐次逼近型　；参考：《南京邮电大学》2017年硕士论文

【摘要】：数字电路的飞速发展以及高效、廉价的优势使其在集成电路领域占据非常重要的位置。现实中很多信号都是未经处理的模拟信号,因此模数转换器作为模拟信号转换成数字信号的重要器件,一直备受关注。逐次逼近模数转换器具有电路结构简单,面积小的优势并且速度和精度适中,模拟电路部分较少,能与快速发展的CMOS工艺相兼容,在低功耗嵌入式系统以及可携带设备中有着广泛的应用。本文实现了一种1MS/s的8位逐次逼近模数转换器电路,数模转换器采用单端结构,可以减少开关数量和降低功耗,同时使用一个dummy电容阵列来弥补时钟馈通和比较器失调电压。比较器是带预放大级的动态比较器,在调节输入失调电压的同时可有效隔离输入和输出。数字时序采用改进型位片式单元(Bit-Slice Unit,BSU)模块实现SAR逻辑,有效减少MOS管数量的同时减少功耗。仿真结果表明,在0.18μm CMOS工艺,采样率为1MS/s的条件下,当输入信号频率为5.86KHz时,SNR为50.1dB,SNDR为49.3d B,SFDR为68.6dB,ENOB为7.89bit,功耗为16.5μW,FOM值为65.8fJ/step。此外,本文还提出了一个基于信号自相关性的低功耗逐次逼近型模数转换器结构。使用比较器比较前后两次采样信号的差值,如果比较结果小于某一阈值则进行较少位数的A/D转换,从而降低A/D转换功耗,并通过仿真验证其可行性。
[Abstract]:With the rapid development of digital circuits and the advantages of high efficiency and low cost, they occupy a very important position in the field of integrated circuits. In reality, many signals are unprocessed analog signals, so analog-to-digital converters, as an important device for the conversion of analog signals to digital signals, have attracted much attention. The successive approximation A / D converter has the advantages of simple circuit structure, small area, moderate speed and accuracy, less analog circuits, and compatible with the rapidly developing CMOS process. It is widely used in low power embedded systems and portable devices. In this paper, an 8-bit successive approximation A / D converter circuit with 1MS / s is implemented. It uses a single terminal structure to reduce the number of switches and power consumption, and uses an dummy capacitor array to compensate for clock feedthrough and comparator offset voltage. The comparator is a dynamic comparator with preamplifier stage, which can effectively isolate input and output while adjusting input offset voltage. The improved Bit-slice Unit-BSUU module is used to realize SAR logic, which can reduce the number of MOS transistors and reduce the power consumption. The simulation results show that in 0.18 渭 m CMOS process with a sampling rate of 1 MS / s, when the input frequency is 5.86 kHz, the SNR is 50.1 dB / s and the SNDR is 49.3 dB / s, the ENOB is 6.89 bit and the power consumption is 16.5 渭 WFOM = 65.8 fJ / s. In addition, a low power successive approximation analog-to-digital converter architecture based on signal autocorrelation is proposed. The comparator is used to compare the difference between the two sampling signals. If the comparison result is less than a certain threshold, the power consumption of the A- / D conversion is reduced, and the feasibility is verified by simulation.
【学位授予单位】：南京邮电大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN792

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