基于低延时电平移位电路的半桥驱动芯片设计

发布时间：2018-06-19 06:10

本文选题：高压半桥驱动芯片 + 高压电平移位电路　；参考：《东南大学》2016年硕士论文

【摘要】：高压半桥驱动芯片,由于其具有高可靠性、低成本、智能化等优点,在白色家电、电动交通工具、中小功率工业设备等领域获得了广泛应用。高压电平移位技术作为高压半桥驱动芯片的核心技术之一,其电路特性将直接影响到半桥驱动芯片的工作性能(传输延时、静态功耗等)和噪声抑制能力(dV/dt噪声及VS负偏压)。因此,对高压电平移位电路的传输特性及可靠性进行系统研究具有重要意义。本文重点分析了半桥驱动芯片电平移位技术,对dV/dt噪声、VS负偏压的产生机理及抑制技术进行了分析,指出了缩短传输延时与提升芯片抗噪可靠性的矛盾,提出了一种有源负载的高压电平移位技术,通过负载阻值的自适应设计,既可以降低噪声在负载上的电压降,又可以有效地降低LDMOS漏端的传输电压,进而降低了负载噪声、提高了高压电平移位电路的VS负压承受能力；其次,分析了高压半桥驱动芯片的延时特性,指出高侧通道中的高压电平移位电路和噪声滤波电路是传输延时的主要来源,采用了一种全差分迟滞比较结构的噪声滤波电路,不仅有效地降低了传输延时,而且有效滤除了dV/dt噪声,最终提升了芯片的抗噪可靠性。基于华润上华的700V 1μm Bipolar-CMOS-DMOS (BCD)工艺,设计了一款采用新型高压电平移位电路的高压半桥驱动芯片,并进行测试。测试结果表明：采用本文高压电平移位电路的半桥驱动芯片,dV/dt噪声能力高达85V/ns,在15V电压下VS负偏压能力达到-10.54V,高侧通道传输延时约93ns。
[Abstract]:Because of its high reliability, low cost and intelligence, high voltage half bridge drive chip has been widely used in white appliances, electric vehicles, medium and small power industrial equipment and so on. As one of the core technologies of high-voltage half-bridge drive chip, the characteristics of high-voltage translation technology will directly affect the performance (transmission delay, static power consumption, etc.) and the noise suppression ability of DV / DT noise and vs negative bias. Therefore, it is of great significance to study the transmission characteristics and reliability of high voltage transposition circuit. In this paper, the level shift technology of half-bridge drive chip is analyzed, and the mechanism and suppression technology of the negative bias voltage of DV / DT noise are analyzed, and the contradiction between shortening the transmission delay and enhancing the reliability of anti-noise of the chip is pointed out. In this paper, a novel high voltage translation technique for active load is proposed. Through the adaptive design of load resistance, the voltage drop of noise on the load can be reduced, and the transmission voltage of LDMOS leakage can be reduced effectively, and then the load noise can be reduced. Secondly, the delay characteristics of the high voltage half-bridge drive chip are analyzed, and it is pointed out that the high voltage translation circuit and the noise filter circuit are the main sources of transmission delay. A noise filtering circuit with fully differential hysteresis comparison structure is adopted, which not only effectively reduces the transmission delay, but also effectively filters out the DV / DT noise, and finally improves the anti-noise reliability of the chip. Based on the 700V 1 渭 m Bipolar-CMOS-DMOS BCDC process, a novel high voltage half-bridge drive chip with a high voltage translation position circuit is designed and tested. The test results show that the half-bridge drive chip based on the high voltage translation circuit has a noise capacity of 85 V / N / DT, a negative bias capacity of -10.54 V at a 15V voltage, and a high side channel transmission delay of about 93ns.The results show that the noise capacity of the half-bridge drive chip is as high as 85V / ns, and the negative bias capacity of the voltage is -10.54V at 15V voltage.
【学位授予单位】：东南大学
【学位级别】：硕士
【学位授予年份】：2016
【分类号】：TN402

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