16位1MSPS逐次逼近型模数转换器设计研究

发布时间：2018-06-19 13:01

本文选题：拆分型ADC + 逐次逼近　；参考：《西安电子科技大学》2015年硕士论文

【摘要】：逐次逼近型模数转换器(SAR ADC)相对流水线模数转换器(Pipeline ADC)和Sigma-Delta模数转换器,具有结构简单,功耗低,面积小等优势,在低频和中频,中等精度场合倍受欢迎。高精度SAR ADC广泛地应用于生物医疗设备,比如CAT扫描仪,便携式血液分析仪,神经传感等设备,工业成像和无线通信等领域。由于电容失配导致的非线性误差成为限制SAR ADC精度的主要因素。标准工艺中,没有校准和修调的SAR ADC能够实现的有效位数一般在12bit以下,校准思想的诞生提升SAR ADC有效位数(ENOB)的空间。在工业界,高精度SAR ADC首先采用激光修条技术和特殊工艺来提高电容匹配精度,再利用校准技术校准电容失配带来的误差。和传统模拟校准相比较,数字校准具有集成度高,面积小,收敛快等优点。因此,数字校准技术成为现在主流的校准技术。本文首先阐述了SAR ADC的基本原理。分析了ADC性能参数,详细地介绍了拆分型ADC基本思想及其工作原理。然后,简单介绍各种冗余位校准算法工作过程,并推导出ADC权重可校准需要满足的条件。为了减小DAC电容网络失配带来的谐波影响,本论文提出一种新思路—将DWA算法用于DAC网络中,实现ADC输出一阶整形。接着,通过对传统“split ADC”后台校准算法原理分析,提出改进型雅克比迭代方法。这种迭代方法具有结构简单,占用硬件资源少,容易实现等优点。由于引入DWA算法,校准算法能够校准各种类型的信号,如直流信号,随机信号,连续信号和非连续信号。对ADC整体结构和“split ADC”后台校准算法进行行为级建模验证,校准算法在600000次量化开始稳定收敛,权重误差在0.5LSB范围之内。系统的静态特性明显提高,校准前ADC的DNL和INL分别为1.5LSB,20LSB,校准后ADC的DNL和INL都在0.5LSB范围之内。随后,论文详细分析了采样保持电路的工作原理,提出了一种新型底极板自举采样开关,设计一款radix2且带有4位冗余算法和DWA算法的电容阵列。此外,论文介绍了比较器失调校准技术,完成一款高精度低噪声双通路的比较器设计和仿真验证。本论文基于SMIC 0.18um 1P6M 3.3V标准CMOS工艺制造实现16位1MS/s SAR ADC。前仿表明:当采样频率为1MS/S,输入频率为0.46582MHZ,摆幅为3.25V的差分信号时,SAR ADC的无散动态范围(SFDR)为102.8dB,有效位数(ENOB)为15.53位。
[Abstract]:The successive approximation analog-to-digital converter (SAR ADCA / D) is relatively pipelined A / D converter (pipeline ADCA / D) and Sigma-Delta A / D converter, which has the advantages of simple structure, low power consumption and small area. It is very popular in low frequency, medium frequency and medium precision situations. High-precision SAR ADC is widely used in biomedical equipment, such as cat scanner, portable blood analyzer, nerve sensor, industrial imaging and wireless communication. The nonlinear error caused by capacitance mismatch is the main factor that limits the precision of SAR ADC. In the standard process, the number of effective bits that can be realized without calibration and modification is generally below 12bit. The birth of calibration idea promotes the space of Enob. In industry, high precision SAR ADC firstly uses laser trimming technology and special technology to improve the accuracy of capacitance matching, and then uses calibration technology to calibrate the error caused by capacitor mismatch. Compared with traditional analog calibration, digital calibration has the advantages of high integration, small area and fast convergence. Therefore, digital calibration technology has become the mainstream calibration technology. In this paper, the basic principle of SAR ADC is introduced. The performance parameters of ADC are analyzed, and the basic idea and working principle of split ADC are introduced in detail. Then, the working process of various redundant bit calibration algorithms is briefly introduced, and the conditions that ADC weights can be calibrated are deduced. In order to reduce the harmonic effect caused by DAC capacitor network mismatch, this paper proposes a new idea, which is to apply DWA algorithm to DAC network to realize the first order shaping of ADC output. Then, by analyzing the principle of the traditional background calibration algorithm, an improved Jacobian iterative method is proposed. This iterative method has the advantages of simple structure, less hardware resources and easy implementation. With the introduction of DWA algorithm, the calibration algorithm can calibrate all kinds of signals, such as DC signal, random signal, continuous signal and discontinuous signal. The whole structure of split and the background calibration algorithm of "split ADC" are modeled and verified at behavioral level. The calibration algorithm starts to converge stably at 600000 quantization, and the weight error is within 0.5 LSB. The DNL and INL of ADC before calibration are 1.5 LSB-20 LSB. after calibration, DNL and INL of ADC are within 0.5LSB range. Then, the working principle of the sampling and holding circuit is analyzed in detail, and a new bottom pole bootstrap sampling switch is proposed, and a capacitive array with 4-bit redundancy algorithm and radix2 algorithm is designed. In addition, this paper introduces the offset calibration technology of comparator, and completes the design and simulation of a comparator with high precision and low noise. In this paper, 16 bit 1MS / s SAR ADCs is realized based on SMIC 0.18um 1P6M 3.3V standard CMOS process. The preform shows that when the sampling frequency is 1MS / S, the input frequency is 0.46582MHZ, and the amplitude is 3.25V, the non-dispersive dynamic range (SFDR) of SAR ADC is 102.8 dB, and the effective bit number is 15.53 bits.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN792

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