SoC可测性设计中低成本与低功耗测试技术研究

发布时间：2018-06-20 13:05

本文选题：SoC测试 + 低成本测试　；参考：《国防科学技术大学》2015年博士论文

【摘要】：随着集成电路与工艺技术的快速发展,片上系统(System-on-a-Chip, SoC)集成密度与复杂性不断增长,嵌入芯核种类繁多,导致SoC芯片测试数据与测试功耗激增,而各芯核集成在SoC芯片内部,无法通过外部I/O端口对其进行直接访问与控制。同时,SoC芯片集成规模不断增加,而芯片管脚数有限,导致内嵌芯核测试面临难以控制和观察等诸多难题,需要内建可测性设计(Design for Testability,DFT)逻辑以提高其可控性和可观性,这会引起SoC测试逻辑和测试时间开销增高。过高的测试成本与测试功耗是SoC测试的两大难题,因此,在SoC可测性设计中,研究低成本与低功耗测试技术成为该领域的热点方向。本文以测试逻辑开销、测试数据、测试应用时间和测试功耗为优化目标,分别在并发在线测试BIST结构、测试数据编码压缩和扫描移位测试功耗等几个方面开展SoC可测性设计中低成本与低功耗测试技术研究,主要研究成果和创新性包括以下几点：1) 提出了一种基于多层解码结构改进的并发在线测试BIST结构及其低硬件开销优化方案。针对多层解码逻辑结构的实现特点,研究并提出一种低硬件开销优化方案,包括输入精简、解码结构改进和模拟退火输入重排序三种优化算法。输入精简用于合并确定性测试集中的相容列,精简需要解码的输入数,以降低解码开销;通过将当前解码划分后剩余不足本级分组列数一半的输入直接传输至下一级解码,改进优化分组以删除部分冗余逻辑；而模拟退火输入重排序对待测电路的输入进行排序优化,以降低解码逻辑开销。实验结果表明,优化后解码逻辑开销在特定测试集与ATALANTA工具生成的测试集上可以分别平均降低20.96%和8.38%,测试成本得到有效降低。此外,对基于多层解码逻辑的并发在线测试BIST结构进行改进,在输出端同样采用类似的多层解码结构对输出响应进行解码验证,使得改进后的BIST结构支持内部逻辑不可见IP核的并发在线测试,适用范围更广2) 提出了两种新的基于块融合和相容性的测试数据编码压缩方案BMC和BM-8C。测试数据量与测试应用时间是测试成本的两个主要因素,本文分析了块融合和9C编码压缩特点,基于块融合和相容性,对测试数据进行块划分并融合连续相容数据块后,在融合块问引入反相容、融合块内引入两个半块相容与反相容等特征构造新的编码测试压缩方案BMC。实验结果表明,BMC编码压缩方案可以获得平均高达68.02%的测试压缩率,且相比于现有方案,测试应用时间开销可以平均降低9.37%。同时,进一步结合9C编码压缩特点,引入融合块内各半块能否能被全0或全1填充等特征进行编码压缩构造新的BM-8C编码压缩方案,以进一步提升测试压缩率并减少测试应用时间。实验结果表明,BM-8C编码压缩方案可以平均获得68.14%的测试压缩率,且测试应用时间开销相对BMC方案平均减少0.73%,实现了低成本测试。此外BMC和BM-8C均为测试无关技术,即其解压缩电路与测试数据选取无关,不需要随着预先确定的测试集改变而进行相应修改。3)面向数据块编码压缩方案,提出一种基于混合粒子群算法的块内重排序优化技术。数据块编码压缩效率很大程度上依赖于数据块内排序,不同的块内排序可能会导致同一测试数据块具有不同编码特征,从而对测试压缩率产生影响。本文研究提出一种基于混合粒子群算法改进的块内重排序优化技术,通过优化数据块内排序,使得更多的数据块具有可以被编码压缩成更短码字的特征,从而减少测试数据存储开销,以提升测试压缩率并降低测试应用时间开销。实验结果表明,经块内重排序优化后,BMC和BM-8C编码压缩方案可以分别获得0.38%和0.43%的测试压缩率提升,而测试应用时间开销分别下降0.82%和2.12%,且不会引入新的测试逻辑开销。4) 基于扫描测试划分,提出一种结合Q-D连接选择性重构策略和测试向量重排序算法的扫描移位测试功耗优化方法。扫描测试划分通过将扫描链划分成等长的多个扫描片段以降低测试数据扫描移位长度,进而减少扫描移位引起的扫描单元翻转数,可以有效降低扫描移位测试功耗。本文基于扫描测试划分研究提出一种结合Q-D连接选择性重构策略和测试向量重排序算法的扫描移位测试功耗优化方法,在各扫描链均匀划分成多个扫描片段后,采用Q-D连接选择性重构各扫描片段内相邻扫描单元问的连接方式,减少扫描移位操作引起的扫描单元冗余翻转数,并通过基于蚁群算法改进的测试向量重排序算法优化测试向量间排序,以降低相邻测试向量间的跳变clash数,进一步降低扫描移位测试功耗。实验结果表明,扫描移位测试功耗经优化后在各扫描链划分成4个和10个扫描片段下分别可以平均降低6.39%和7.64%,且提出的优化方法不会对原有测试质量、测试成本以及待测电路的性能造成影响,并适用于所有扫描测试结构。
[Abstract]:With the rapid development of integrated circuits and technology, the integrated density and complexity of System-on-a-Chip (SoC) is increasing, and there are a wide variety of core cores, which results in a surge in testing data and test power of SoC chips, and core cores are integrated inside the SoC chip, and can not be directly accessed and controlled by the external I/O port. The size of SoC chip is increasing, and the number of chip pins is limited, which leads to the difficult control and observation of embedded core core testing. The Design for Testability (DFT) logic is needed to improve its controllability and observability. This will cause the higher cost of testing logic and test time of SoC and the high test cost. And test power consumption is the two difficult problem of SoC test. Therefore, in SoC testability design, the research of low cost and low power testing technology has become a hot topic in this field. This paper is based on test logic overhead, test data, test application time and test power consumption as the optimization target, and the BIST structure of concurrent on-line testing and test data coding compression respectively. The research of low cost and low power testing technology in SoC testability design is carried out in several aspects, such as scanning shift test power consumption. The main research results and innovation include the following points: 1) an optimization scheme for concurrent on-line test BIST based on multi-layer decoding structure and its low hardware cost optimization is proposed. A low hardware overhead optimization scheme is proposed, including three optimization algorithms for low hardware overhead, including input simplification, decoding structure improvement and simulated annealing input reordering. Input simplification is used to merge the compatible columns in a deterministic test set, streamline the input number needed to decode, and reduce the decoding overhead; by dividing the current decoding, it is divided after the current decoding. The input of half of the remaining sub class columns is transferred directly to the next level decoding, and the optimization packet is improved to delete partial redundant logic. The simulated annealing input reordering is used to sort the input of the test circuit to reduce the decoding logic overhead. The experimental results show that the decoding logic overhead is in a specific test set and ATALANT after the optimization. The test set generated by A tools can be reduced by 20.96% and 8.38% on average, and the cost of testing is reduced effectively. In addition, the BIST structure of concurrent online testing based on multi-layer decoding logic is improved. The output response is decode and validate the output response with similar multilayer decoding structure at the output end, making the improved BIST structure support inside. The Department logic can not see the concurrent online testing of IP kernel. The application scope is more wide 2) two new test data coding compression schemes based on block fusion and compatibility are proposed, BMC and BM-8C. test data amount and test application time are the two main factors of test cost. This paper analyzes block fusion and 9C coding compression characteristics, block fusion and block fusion. After block partition and fusion of continuous compatible data blocks for test data, a new coding test compression scheme is constructed in the fusion block to construct a new coding test compression scheme with 2.5 blocks of compatibility and anti compatibility in the fusion block. The results show that the BMC coding compression scheme can obtain an average of up to 68.02% of the test compression rate and phase of the BMC.. Compared with the existing scheme, the time overhead of test application can be reduced 9.37%. at the same time, and further combined with the features of 9C coding compression, a new BM-8C coding compression scheme can be constructed by introducing the features of all 0 or all 1 filling blocks in the fusion block, in order to further improve the test compression rate and reduce the test application time. The results show that the BM-8C coding compression scheme can obtain an average of 68.14% test compression rate, and the test application time cost is 0.73% less than the BMC scheme, and the BMC and BM-8C are all test independent techniques, that is, the decompression circuit is independent of the test data selection, and does not need to be changed with the pre determined test set. The corresponding modification.3) oriented data block coding and compression scheme, a kind of intra block reordering optimization technique based on Hybrid Particle Swarm Optimization (PSO) is proposed. The compression efficiency of data block coding is largely dependent on the sorting in the data block. The different block sorting may lead to the same test data block with different coding features, so that the test pressure can be tested. In this paper, an improved intra block reordering optimization technique based on Hybrid Particle Swarm Optimization (PSO) is proposed in this paper. By optimizing the data block sorting, more data blocks can be compressed into shorter codewords, thus reducing the test data storage opening, in order to improve the test compression rate and reduce the test application. The experimental results show that the BMC and BM-8C coding compression schemes can gain 0.38% and 0.43% test compression rates respectively after the block reordering optimization, while the test application time costs are reduced by 0.82% and 2.12% respectively, and the new test logic overhead is not introduced,.4) based on the scan test division, and a combination of Q-D connection selectivity is proposed. The scanning shift test power optimization method of the reconfiguration strategy and the test vector reordering algorithm. The scanning test division can reduce the scan shift length by dividing the scan chain into multiple scan segments to reduce the scan shift length of the test data, and reduce the scan shift unit turnover. This paper can effectively reduce the power consumption of the scan shift test. A scanning shift test power optimization method, which combines the Q-D connection selective reconfiguration strategy and the test vector reordering algorithm, is proposed. After the scan chain is divided into multiple scan segments, the Q-D connection is used to selectively reconstruct the connection mode of the adjacent scanning unit in the scanned segments and reduce the scan. In order to reduce the number of jump clash between adjacent test vectors and further reduce the power of scanning shift test, the experiment results show that the power of scanning shift test is optimized in each scan chain. The average reduction of 4 and 10 scanning segments can be reduced by 6.39% and 7.64% respectively, and the proposed optimization method will not affect the original test quality, the test cost and the performance of the circuit to be measured, and it is suitable for all the scanning test structures.
【学位授予单位】：国防科学技术大学
【学位级别】：博士
【学位授予年份】：2015
【分类号】：TN407

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