基于PCIE接口的IPSec加速SoC设计

发布时间：2018-06-21 07:33

  本文选题：IPSec协议 + SoC　； 参考：《计算机工程与设计》2017年05期

【摘要】：为达到IPSec实现的高速性、灵活性以及安全性,设计一个IPSec加速SoC。引入高速PCIE接口突破主机与SoC通信速度瓶颈;采取多核设计技术和层次化存储结构,构建以交叉存储为主的高速数据交换区和以邮箱为主的引擎间状态通信区;采用指令级并行和流水线并行技术,对IPSec协议中算法进行多核映射。实验结果表明,该SoC对于IPSec中典型分组密码算法AES的吞吐率可达1Gbps,对于认证算法SM3可达2Gbps,较好地满足了高速网络处理需求。
[Abstract]:In order to achieve the high speed, flexibility and security of IPSec implementation, an IPSec accelerated SoC is designed. High speed PCIE interface is introduced to break through the bottleneck of communication speed between host computer and SoC, and multi-core design technology and hierarchical storage structure are adopted to construct high speed data exchange area based on cross storage and state communication area between engines based on mailbox. Instruction level parallelism and pipeline parallelism are used to map the algorithms in IPSec protocol. Experimental results show that the throughput of the SoC to AES, a typical block cipher algorithm in IPSec, can reach 1Gbpsand to the authentication algorithm SM3 up to 2Gbpss.This SoC can better meet the needs of high-speed network processing.
【作者单位】： 信息工程大学;
【分类号】：TN402
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本文编号：2047752