一种8位低功耗模数转换器设计与实现

发布时间：2018-06-21 08:16

本文选题：ADC + DAC　；参考：《中国科学院大学(中国科学院工程管理与信息技术学院)》2017年硕士论文

【摘要】：ADC(ADC Analog to Digital Converter)是实现模拟信号转换成数字信号的功能IP(Intellectual Property),ADC可以将模拟信号的连续变量转换成数字信号的离散变量,是联系SOC(System On Chip)中数字模块和模拟模块的桥梁。在CMOS(Complementary Metal Oxide Semiconductor)工艺下,越来越多的SOC采用数模混合集成。ADC的性能参数以及ADC与数字系统兼容程度也越来越受到重视,对ADC的研究也越来越多。目前设计低于5Msps(Million Samples per Second MS/s)分辨率的ADC应用一般采用SAR(successive approximation)数模转换器结构。对比流水线ADC或闪烁(Flash)ADC,SAR结构具有功耗低、面积小、速度快等优点。本课题主要设计和实现了一款基于电荷型SAR结构的8位低功耗ADC。电荷型SAR结构具有速度快、功耗低等特点。本课题设计的主要工作分为高精度DAC(Digital to Analog Converter)设计、高精度比较器设计和数字控制逻辑设计。在高精度DAC设计中,采用分段电容结构。在比较器设计中,采用NP并联结构,能达到较高的增益和精度。数字控制逻辑设计采用ASIC设计,并加入沉睡模式等降低功耗的设计方法。本课题基于SMIC 40nm LL(low-leakage)CMOS工艺设计,并采用前仿真和后仿真相结合的方法来进行电路和版图设计。仿真结果表明:该ADC在模拟电压为1.8V、数字电压为1.1V的情况下,采样精度达到1Msps,最小分辨率5mv,功耗1mw,面积为150umX150um。该ADC达到了预期设计目标。
[Abstract]:ADCA Analog to digital conversion is the function of converting analog signal into digital signal. It can convert the continuous variable of analog signal into discrete variable of digital signal. It is also a bridge between digital module and analog module in SOCU system on chip. In the CMOS complementary Metal Oxide Semiconductors process, more and more SOC uses the performance parameters of digital-analog hybrid integration. ADC and the compatibility of ADC with digital systems are paid more and more attention to, and more research on ADC. At present, ADC applications with a resolution of less than 5Mspsllion samples per second MS / s generally use SARX succeed approval converter (DAC) architecture. Compared with pipelined ADC or flash ADC-SAR structure, it has the advantages of low power consumption, small area and high speed. In this paper, an 8 bit low power ADCs based on charge-type SAR structure is designed and implemented. The charge-type SAR structure is characterized by high speed and low power consumption. The main work of this paper is divided into three parts: high precision digital to Analog conversion design, high precision comparator design and digital control logic design. In the design of high precision DAC, the piecewise capacitance structure is adopted. In the design of comparator, NP parallel structure is used to achieve high gain and precision. The design of digital control logic adopts ASIC design and adds sleeping mode to reduce power consumption. This thesis is based on SMIC 40nm LLL low-leakage CMOS process design, and adopts the method of combining pre-simulation and post-emulation to design the circuit and layout. The simulation results show that when the analog voltage is 1.8 V and the digital voltage is 1.1 V, the sampling accuracy is 1 Msps, the minimum resolution is 5 MV, the power consumption is 1 MW, and the area is 150 umX 150 um. The ADC achieves the desired design goal.
【学位授予单位】：中国科学院大学(中国科学院工程管理与信息技术学院)
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN792

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