65nm工艺下一种新型单粒子多瞬态测试系统的研究与设计

发布时间：2018-06-21 14:27

本文选题：单粒子瞬态 + 单粒子多瞬态　；参考：《国防科学技术大学》2015年硕士论文

【摘要】：随着中国综合国力的进一步提升,航天航空器材和武器装备对国产抗辐射芯片的需求越来越迫切。抗辐射集成电路和辐射效应的研究吸引着越来越多的学者们加入其中,同时也成为了该领域研究的重点课题之一。随着纳米CMOS集成电路的不断发展,半导体器件的辐射效应特性也发生着多方面的变化,其中以单粒子瞬态尤为明显。到纳米工艺下,单粒子瞬态(SET)已经成为了辐射电路中系统软错误出现的主要来源,同时也是新纳米工艺下集成电路抗辐射加固的研究重点。在纳米CMOS集成电路中,器件的特征尺寸更小、集成密度更大、节点相距更近。这使得单个高能粒子的入射可能导致多个节点的电荷收集,使SET的产生机理与以往的研究相比会出现许多新的情况,SET在传播中也随之出现一些新的现象。单粒子导致的多节点电荷共享现象,将可能出现单粒子多瞬态(SEMT)和单粒子脉冲窄化(SET Quenching),这些在65nm CMOS集成电路中已成为普遍现象。在新工艺节点下,单粒子多瞬态的研究工作变得日益重要,研究价值也越发的明显。本文将针对SEMT的试验测试技术展开一系列的研究工作,解决了新工艺节点下SEMT试验表征的技术问题。本文提出了一种新型单粒子多瞬态测试系统,并且在65nm工艺下设计了测试芯片,通过重离子辐射试验证明了此测试系统在SEMT试验研究方面的可行性,在解决SEMT试验表征技术问题方面是一个创新。关于SEMT测试系统的研究,本文做了一些具体研究工作,并取得了一定的研究成果:⑴提出了一种SEMT测量电路。本文在单链SET测量技术的研究基础之上,提出了一种新型SEMT测量电路。此测量电路既保证了单个SET的测量精度,又实现了多SET的同时捕获,实现了SEMT的高精度自触发扫描捕获。这种SEMT测量电路对时序控制要求严格,并且还进行了抗辐射加固设计。⑵设计了新的轰击单元。以往的SET研究都是以反相器链作为被测电路,根据不同的研究目的在版图和电路方面做相应的处理。为了将PMOS器件和NMOS器件中的SEMT分别表征,本文设计了P-hit和N-hit轰击单元;为了研究源极注入效应在多节点电荷共享收集中的作用,提出了改进型的P-hit和N-hit轰击单元。⑶提出了一种SEMT被测电路结构。依据以往的研究经验,提出了一种纵向交错布局的多短链SEMT被测电路结构。试验结果表明,该电路结构既保证了SEMT产生的合理性,又保证了单个SET测量的精确性。⑷实现了SEMT测试芯片,并设计了地面辐射试验测试系统。将研究提出的SEMT测量电路和被测电路在65nm体硅CMOS工艺下实现了SEMT测试芯片,并且成功流片。在以往的辐射试验研究基础之上,针对SEMT测试芯片的辐射试验设计了具体的试验测试系统,并完成了一次重离子辐射试验。试验结果表明:此SEMT测试系统完全能够实现纳米CMOS电路中SEMT的试验表征,这将为SEMT的研究提供新的试验方法,为进一步深入研究纳米电路中单粒子瞬态提供了有效地研究手段和科学地试验依据。
[Abstract]:With the further improvement of China's comprehensive national strength, the demand of aerospace equipment and weapons to domestic radiation chips is becoming more and more urgent. Research on integrated circuits and radiation effects has attracted more and more scholars to join, and it has also become one of the key topics in this field. With the nano CMOS integrated circuit With the continuous development of the semiconductor devices, there are many changes in the radiation effects of semiconductor devices, in which the single particle transient is particularly obvious. Under the nanotechnology, the single particle transient (SET) has become the main source of the soft error in the radiation circuit, and is also the focus of the research on the anti radiation reinforcement of the integrated circuits under the new nanotechnology. In nanoscale CMOS integrated circuits, the characteristic size of the device is smaller, the integration density is larger, the node distance is closer. This makes the incidence of a single high-energy particle may lead to the collection of the charge of multiple nodes, so that there will be a lot of new situations in the generation mechanism of the SET and the previous research, and the SET will also appear some new phenomena in the transmission. The phenomenon of multi node charge sharing caused by sub nodes will be likely to appear single particle multiple transient (SEMT) and single particle pulse narrowing (SET Quenching). These have become a common phenomenon in the 65nm CMOS integrated circuit. Under the new technology node, the research work of single particle and multi transient is becoming more and more important and the research value is more obvious. This paper will be aimed at SEMT A series of research work has been carried out to solve the technical problems of SEMT test characterization under the new process node. A new single particle multi transient test system is proposed in this paper, and the test chip is designed under the 65nm process. The feasibility of the test system in the SEMT test research is proved by the heavy ion radiation test. It is an innovation in solving the technical problems of SEMT test characterization. On the research of SEMT testing system, this paper has done some specific research work and obtained some research results: (1) a kind of SEMT measurement circuit is proposed. Based on the study of single strand SET measurement technology, a new type of SEMT measurement circuit is proposed. The measurement circuit not only ensures the measurement accuracy of a single SET, but also realizes the simultaneous capture of multiple SET, and realizes the high precision self triggered scan capture of SEMT. This SEMT measurement circuit is strict with the timing control, and has also carried out the design of anti radiation reinforcement. (2) the new bombardment unit is designed. The former SET research has been measured as the inverter chain. In order to characterize the PMOS and the SEMT in the NMOS devices, the P-hit and the N-hit bombardment units are designed in this paper. In order to study the role of the source injection effect in the collection of multi node charge sharing, an improved P-hit and N-hit bombardment unit is proposed. A kind of SEMT measured circuit structure is presented. Based on previous research experience, a multi short chain SEMT circuit structure with longitudinal staggered layout is proposed. The experimental results show that the circuit structure not only ensures the rationality of the SEMT production, but also ensures the accuracy of the single SET measurement. 4. The SEMT test chip is realized and the ground radiation test is designed. The SEMT measurement circuit and the measured circuit proposed in this paper have realized the SEMT test chip under the 65nm body silicon CMOS technology and the successful flow sheet. On the basis of the previous radiation test, the specific test system was designed for the radiation test of the SEMT test chip, and a heavy ion radiation test was completed and the test junction was completed. The results show that the SEMT test system can fully realize the test characterization of SEMT in the nano CMOS circuit. This will provide a new test method for the study of SEMT, and provide effective research means and scientific test basis for further study of single particle transient in nanoscale circuits.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN40

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