FPGA时序收敛分析及仿真

发布时间：2018-06-23 09:39

本文选题：现场可编程门阵列 + 时序收敛　；参考：《中国科学院研究生院（光电技术研究所）》2015年硕士论文

【摘要】：现场可编程门阵列FPGA在其出现三十年内发展迅速,其在灵活度,开发周期以及开发成本上的优势使得FPGA被广泛使用在各个领域。而随着FPGA设计朝着大规模、高性能方向发展,其时序收敛问题日益成为FPGA设计中的重要问题。本文主要就FPGA时序收敛性进行了分析和仿真。本文在介绍了FPGA内部的结构和其时序资源的基础上,就FPGA时序电路的基础进行了研究和建模,并将其引入到FPGA时序分析中,针对FPGA的各种时序路径进行时序分析,主要研究了FPGA输入输出时序,同步逻辑时序,异步逻辑时序这三个方面。同时本文也从同步逻辑时序优化,异步逻辑时序优化化以及代码风格三个方面对FPGA时序设计进行探讨。本文以DDR2 SDRAM接口控制器为研究对象进行详尽的时序分析。DDR2 SDRAM是一类高速存储器,其数据速率是时钟频率的两倍,同时在与FPGA进行数据传输时,数据在不同时钟域间的传输将对整个系统的时序产生影响。故本文主要通过时序分析的形式研究了控制器的数据通道的设计及其数据在不同时钟域间传输的同步过程,同时对数据通道及其同步过程进行时序仿真,并通过相关时序约束和静态时序分析报告分析了控制器的时序性能。
[Abstract]:Field Programmable Gate Array (FPGA) has developed rapidly in the past 30 years. Its advantages in flexibility, development cycle and development cost make it widely used in various fields. With the development of FPGA design in the direction of large scale and high performance, the timing convergence is becoming an important problem in FPGA design. In this paper, the timing convergence of FPGA is analyzed and simulated. On the basis of introducing the internal structure of FPGA and its timing resources, this paper studies and models the basis of FPGA sequential circuit, and introduces it into FPGA timing analysis, and carries out timing analysis for all kinds of timing paths of FPGA. This paper mainly studies three aspects of FPGA input and output timing, synchronous logic timing and asynchronous logic timing. At the same time, this paper also discusses FPGA timing design from three aspects: synchronous logic timing optimization, asynchronous logic timing optimization and code style. This paper takes DDR2 SDRAM interface controller as the research object to carry on detailed timing analysis. DDR2 SDRAM is a kind of high speed memory, its data rate is twice the clock frequency, at the same time, when it transfers data with FPGA, The transmission of data between different clock domains will affect the timing of the whole system. So this paper mainly studies the design of the controller data channel and the synchronization process of the data transmission between different clock domains through the form of time sequence analysis, and carries on the time sequence simulation to the data channel and its synchronization process at the same time. The timing performance of the controller is analyzed by correlation timing constraints and static timing analysis reports.
【学位授予单位】：中国科学院研究生院（光电技术研究所）
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN791

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