面向应用的可重构片上网络设计与实现

发布时间：2018-06-25 11:36

本文选题：片上网络 + 面向应用　；参考：《西安电子科技大学》2015年硕士论文

【摘要】：基于片上总线的SoC设计存在全局时钟难以同步、可扩展性和可重用性较差、通讯效率较低等问题,严重制约了集成在单芯片上的IP核规模和系统性能。片上网络NoC是将分布式计算网络的思想用于复杂的SoC设计,能够实现高效互连并解决SoC的通信问题。然而,传统片上网络难以适应复杂应用通信多样性的需求,易发生网络拥塞现象,数据传输和通信能力有限。相比之下,可重构片上网络具有更好的灵活性和可配置性,当网络中出现拥塞或发生故障时,它可以静态或者动态地重构片上网络的拓扑结构、路由器结构或者链路方向等,以缓和拥塞或解决故障,提高片上网络的通信能力。本文提出一种新的面向应用的可重构片上网络AORNoC,针对不同应用,提供一种全局优化的路径配置,减少网络拥塞度。本方案将传统片上网络中的计算逻辑和控制逻辑分离,以软件形式实现全局路径分配算法,在通信任务图映射到片上网络的拓扑结构上后,采用该算法并利用映射所生成的完整地址信息来实现网络的路径预计算功能。计算结果转换为编码形式配置给各个路由器或通信控制器,以此建立起其各输入输出端口之间的对应连接关系,从而完成片上网络通信路径分配。另外,通过动态重构路由器的编码信息,可以针对不同应用实现高效路径分配。全局路径分配算法是在自适应转弯模型上加入多向协商控制算法来降低全局路径拥塞度,同时为每个源节点设置一组可行注入方向集合,该集合包含源数据初始注入方向和备选注入方向两种元素,可以增大路径分配的多样性。本文实现的路由器和通信控制器结构均与其传统结构不同,以编码信息配置模块替代了传统的路由计算单元,从输入端口进来的微片可以直接从该模块中获取相应的输出信息。本文分别基于2D Mesh和SRNoC拓扑结构搭建了4×4和8×8两种规模的AORNoC,并采用基于开环互连网络测量方式的性能评测平台对AORNoC进行性能评测,并将其结果与传统片上网络进行了对比。结果表明,AORNoC具有更好的延迟特性和更少的面积开销,在transpose1、transpose2、bit-reversal、shuffle、butterfly业务分布下,基于2D Mesh拓扑结构的8×8的AORNoC相比于传统片上网络XY、Oddeven和NoP,饱和负载各平均提升了65.4%、27.4%和44.6%;基于SRNoC拓扑结构的8×8的AORNoC,相比于传统片上网络SRNoC,饱和负载平均增幅为54.4%。因此,AORNoC可以提供更好的路径配置,实现更好的网络通信和数据传输能力。
[Abstract]:SoC design based on on-chip bus has some problems, such as hard to synchronize global clock, poor scalability and reusability, and low communication efficiency, which seriously restricts the scale and system performance of IP core integrated on a single chip. The idea of distributed computing network is used in complex SoC design, which can efficiently interconnect and solve the communication problem of SoC. However, the traditional on-chip network is difficult to adapt to the diversity of complex applications, is prone to network congestion, and has limited data transmission and communication capacity. In contrast, the reconfigurable on-chip network is more flexible and configurable. When there is congestion or failure in the network, it can reconstruct the topology, router structure or link direction of the on-chip network statically or dynamically. To ease congestion or troubleshooting, improve the communication capacity of the on-chip network. In this paper, a new application-oriented reconfigurable on-chip network AORNoC is proposed, which provides a globally optimized path configuration for different applications and reduces network congestion. In this scheme, the computational logic and control logic in the traditional on-chip network are separated, and the global path assignment algorithm is implemented in the form of software. After the communication task diagram is mapped to the topology structure of the on-chip network, Using this algorithm and the complete address information generated by the mapping, the network path precomputing function is realized. The results are converted into coding configuration to each router or communication controller, and the corresponding connection relationship between the input and output ports is established, thus the on-chip network communication path allocation is completed. In addition, by dynamically reconstructing the encoding information of routers, efficient path allocation can be realized for different applications. Global path assignment algorithm is to add multi-direction negotiation control algorithm to adaptive turning model to reduce global path congestion and set a set of feasible injection directions for each source node. The set consists of two elements: the initial injection direction of the source data and the alternative injection direction, which can increase the diversity of path allocation. The router and communication controller structure implemented in this paper are different from their traditional structure. The encoding information configuration module is used to replace the traditional routing computing unit. The microchip coming in from the input port can obtain the corresponding output information directly from the module. In this paper, based on 2D mesh and SRNoC topologies, AORNoC of 4 脳 4 and 8 脳 8 is built, and the performance of AORNoC is evaluated by an open-loop network measurement platform, and the results are compared with the traditional on-chip network. The results show that AORNoC has better delay characteristics and less area overhead. The saturation load of 8 脳 8 AORNoC based on 2D mesh topology is increased by 65.4% and 44.6%, respectively, compared with the traditional on-chip network XYYOOddeven and NoP, and the saturation load of 8 脳 8 AORNoC based on SRNoC topology is 54.4% higher than that of the traditional on-chip network SRNoC. Therefore, AORNoC can provide better path configuration and better network communication and data transmission capability.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN47

【相似文献】