基于FPGA的全数字锁相环设计与研究

发布时间：2018-06-27 05:04

本文选题：FPGA + EDA　；参考：《安徽大学》2015年硕士论文

【摘要】：随着电子技术和信息科学的快速发展,锁相环技术在突破了很多技术困难的同时,其应用领域也在不断的扩大,从原先在航天领域的应用,如今,锁相环已深入军事、医疗、工业设计等诸多领域,目前,锁相环已经成为大规模集成电路、片上系统等高质量电子设备中不可或缺的模块。数字锁相环的出现,使锁相环的性能飞速提升,它很好地克服了模拟锁相环遇到的直流部件饱和、零点漂移以及需要进行初始校准等一系列的问题。随着集成电路技术的日益精进,全数字锁相环(ADPLL)相继问世,这种锁相环各个模块的结构全部由数字电路组成,并且具备实时处理能力,以及具有抗干扰性强、体积小和可靠性高等优点。鉴于此,论文设计了一种增减量可变计数式全数字锁相环的结构,并对该锁相环进行了电路设计和仿真分析。论文研究的主要工作如下：(1)对锁相环各部件的结构与性能进行了系统分析和研究,提出了基于增减量可变计数式全数字锁相环结构设计方案；(2)对全数字锁相环的各模块进行了详细的结构设计与电路设计,并且进行了仿真综合；(3)基于上述各个模块的电路设计和仿真,进而实现了整体结构设计与对比仿真分析。从仿真结果得出,此改进型全数字锁相环具有锁定速度快、易于集成及控制灵活等优点。
[Abstract]:With the rapid development of electronic technology and information science, phase locked loop (PLL) technology has broken through a lot of technical difficulties, and its application fields have also been continuously expanded. From the original application in the space field, now PLL has been deeply used in military and medical treatment. At present, phase locked loop (PLL) has become an indispensable module in high quality electronic devices such as large scale integrated circuits, on-chip systems and so on. The appearance of digital phase-locked loop (DPLL) makes the performance of PLL improve rapidly. It overcomes a series of problems such as DC component saturation zero drift and initial calibration of analog PLL. With the development of integrated circuit technology, all digital phase-locked loop (ADPLL) has come out one after another. The structure of each module of this kind of PLL is composed of digital circuit, and it has real-time processing ability and strong anti-jamming ability. Small size and high reliability and other advantages. In view of this, this paper designs a structure of all digital PLL with variable increment and decrease quantity, and carries on the circuit design and simulation analysis to the PLL. The main work of this paper is as follows: (1) the structure and performance of PLL components are systematically analyzed and studied, and a scheme of all-digital PLL structure design based on variable count is proposed. (2) the structure design and circuit design of all digital PLL modules are carried out in detail, and the simulation synthesis is carried out. (3) the circuit design and simulation based on the above modules are implemented, and the overall structure design and comparative simulation analysis are realized. The simulation results show that the improved all-digital PLL has the advantages of fast locking speed, easy integration and flexible control.
【学位授予单位】：安徽大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN911.8;TN791

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