基于STorus的光片上网络的设计与研究

发布时间：2018-06-29 08:29

本文选题：光片上网络 + STorus　；参考：《西安电子科技大学》2015年硕士论文

【摘要】：随着人们对通信需求的日益增大,高性能处理器的研究日渐受到追捧。特别是近几年,片上网络(Network-on-Chip,NoC)在数据处理方面的表现越来越突出,集成到单个芯片上的IP核越来越多。但是,当集成规模过大时,基于电互连的片上网络在时延、能耗、电磁干扰等诸多方面会遭遇发展瓶颈。硅光技术的发展及纳米光器件研究的进步使得光片上网络(Optical Network-on-Chip,ONoC)的实现成为可能,光片上网络的提出可以有效解决现阶段电片上网络中存在的时延、带宽及电磁干扰等问题。本文首先介绍了片上网络的兴起原因和发展过程,分析了光片上网络的优势。接着展示了现阶段光片上网络的研究进展,从光器件、交换机制、路由算法、拓扑结构等几个方面对光片上网络的现状进行了研究。现有光片上网络架构多采用mesh和torus拓扑,在网络的直径、能耗、芯片面积等方面存在性能瓶颈。针对这些问题我们提出了一种新型的光片上网络架构-STorus,STorus充分考虑了跳数、直径和光损耗等多方面因素。STorus采用了双子网架构,每个子网使用两类扭环,从而大大减小了网络直径和跳数。在网络布局方面使用硅穿孔(Through Silicon Via,TSV)技术,两个子网中走势相同的波导布局在同一光层,整个网络的波导分成两个光层,由此大大减小了光损耗。论文采用OPNET仿真软件对整个网络进行了时延、吞吐的仿真,并详细分析了网络的能耗、直径等。仿真结果表明,和传统的mesh、torus相比,STorus在损耗、网络直径、时延及吞吐等方面都具有优异的性能。随着片上集成的IP核数目的增多,存储访问的次数增多,存储带宽成为片上网络存储访问的一大问题。如果存储带宽不能满足处理器核的请求速率,系统的性能将会受到很大影响。因此,论文进一步研究了存储控制器在STorus中的接入位置对存储访问的影响,优化了存储控制器在STorus中的接入位置。仿真结果表明,在同等网络规模下,使用相同数目的存储控制器时,优化的接入位置可使网络性能更佳。
[Abstract]:With the increasing demand for communication, the research of high performance processors is becoming more and more popular. Especially in recent years, the performance of Network-on-ChipNOC in data processing has become more and more outstanding, and more IP cores have been integrated into a single chip. However, when the integration scale is too large, the on-chip network based on electrical interconnection will encounter bottlenecks in many aspects, such as delay, energy consumption, electromagnetic interference and so on. With the development of silicon optical technology and the development of nano-optical devices, the realization of optical network-on-ChipONoC (ONoC) is possible. The proposed optical on-chip network can effectively solve the problems such as delay, bandwidth and electromagnetic interference existing in the on-chip network at present. In this paper, the rise and development of on-chip network are introduced, and the advantages of optical on-chip network are analyzed. Then, the research progress of optical on-chip network is presented. The current situation of optical on-chip network is studied from optical devices, switching mechanism, routing algorithm, topology and so on. Mesh and torus topologies are used in the existing optical network architecture, and there are performance bottlenecks in network diameter, energy consumption, chip area and so on. In order to solve these problems, we propose a new type of optical on-chip network architecture-STorus, which takes into account many factors, such as hops, diameters and optical losses. STorus adopts a two-subnet architecture, and each subnet uses two types of torsion loops. Thus, the network diameter and hops are greatly reduced. In the aspect of network layout, through Silicon via (TSV) technology is used. The waveguide with the same trend in two subnets is arranged in the same optical layer, and the waveguide of the whole network is divided into two optical layers, which greatly reduces the optical loss. In this paper, OPNET simulation software is used to simulate the delay and throughput of the whole network, and the energy consumption and diameter of the network are analyzed in detail. The simulation results show that compared with the traditional meshtorus, SSTorus has excellent performance in loss, network diameter, delay and throughput. With the increase of the number of IP cores integrated on a chip, the number of memory access increases, and the storage bandwidth becomes a major problem of on-chip network storage access. If the storage bandwidth can not meet the request rate of the processor core, the performance of the system will be greatly affected. Therefore, the influence of the access location of the memory controller in STorus on the memory access is further studied, and the access location of the storage controller in the STorus is optimized. The simulation results show that under the same network size and the same number of memory controllers, the optimal access location can make the network performance better.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN47

【相似文献】