3D-ICs优化TSV和叶子节点数量的扫描树设计

发布时间：2018-07-02 07:40

本文选题：三维集成电路 + 扫描树　；参考：《合肥工业大学》2015年硕士论文

【摘要】：随着三维集成电路(Three-Dimensional Integrated Circuits,3D-ICs)的不断发展,测试在集成电路的实现过程中是必不可少的环节。基于扫描的可测试性设计(Design for Testability, DFT)的多扫描链设计改善了单扫描链设计的测试应用时间,但其测试数据量并未减少,继而提出扫描树设计方法用来减少测试应用时间及测试数据量。扫描链设计的测试应用时间由最长的扫描链的长度决定的,扫描树结构降低了最长扫描链的长度,从而减少测试应用时间和测试数据量。在三维集成电路的扫描树设计过程中,一方面层与层间的扫描单元的连接需要硅通孔(Through Silicon Via, TSV),但目前制造工艺还不够成熟,TSV制造成本较高。另一方面扫描树的叶子节点需要连接到扫描输出端口,决定了测试引脚的数量以及测试响应数据量,故而为了降低三维集成电路的测试成本,本文就TSV数量及扫描树的叶子节点数量这两个因素,研究了以下两种三维集成电路的扫描树结构：首先,提出一种在扫描树的叶子节点数量约束下优化TSV数量的三维集成电路单扫描树设计方法。采用整数线性规划(Integer Linear Programming, IL P)算法,构建在不同的扫描树叶子节点数的约束下最小化TSV数量的三维集成电路单扫描树ILP模型。实验表明,与已有的三维集成电路单扫描树设计方法相比,在相同叶子节点数量的情况下,本文所提方法能够有效地减少TSV数量。其次,为了进一步减少测试应用时间,在单扫描树设计的基础上,构建三维集成电路多扫描树的ILP模型,并在TSV数量的约束下优化多扫描树的叶子节点数量。根据实验结果分析,相比于单扫描树结构,多扫描树结构的叶子节点数量最优时与单扫描树的叶子节点数相差不多,TSV数量成倍的增加了,但大大减少了多扫描树的测试应用时间。本文提出的单扫描树结构有效地减少了TSV数量,多扫描树结构有效地减少了叶子节点数量和测试应用时间。
[Abstract]:With the development of Three-dimensional Integrated Circuits (3D-ICs), testing is an essential part in the implementation of integrated circuits. The design of multi-scan chain based on Design for Testability (DFT) improves the test application time of single scan chain design, but the amount of test data is not reduced. Then a scanning tree design method is proposed to reduce the test application time and test data. The test application time of scan chain design is determined by the length of the longest scan chain. The scan tree structure reduces the length of the longest scan chain, thus reducing the test application time and the amount of test data. In the process of scanning tree design of 3D integrated circuits, on the one hand, the connection between layers and layers requires through Silicon via (TSV), but at present the manufacturing process is not mature enough to produce TSV. On the other hand, the leaf nodes of the scan tree need to be connected to the scan output port, which determines the number of test pins and the amount of test response data. In this paper, the following two kinds of scanning tree structures of 3D integrated circuits are studied: firstly, the number of TSV and the number of leaf nodes of the scan tree are studied. A single scan tree design method for 3D integrated circuits is proposed to optimize the number of TSV under the constraint of the number of leaf nodes in the scan tree. An integer linear programming (IL P) algorithm is used to construct a single scan tree ILP model for 3D integrated circuits, which minimizes the number of TSV nodes under the constraints of the number of leaf nodes in different scan trees. The experimental results show that the proposed method can effectively reduce the number of TSV in the case of the same number of leaf nodes compared with the existing single scan tree design method for 3D integrated circuits. Secondly, in order to further reduce the test application time, the ILP model of 3D integrated circuit multi-scan tree is constructed on the basis of single scan tree design, and the number of leaf nodes of multi-scan tree is optimized under the constraint of TSV number. According to the experimental results, compared with the single scan tree structure, when the number of leaf nodes of the multi-scan tree structure is optimal, the number of TSV increases exponentially when the number of leaf nodes of the multi-scan tree is the same as that of the single scan tree. However, the test application time of multi-scan tree is greatly reduced. The single scan tree structure proposed in this paper can effectively reduce the number of TSV, and the multi-scan tree structure can effectively reduce the number of leaf nodes and test application time.
【学位授予单位】：合肥工业大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN402

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