一种基于分段电容的低功耗SARADC设计

发布时间：2018-07-04 23:50

本文选题：逐次逼近型模数转换器 + 低功耗　；参考：《天津大学学报(自然科学与工程技术版)》2017年08期

【摘要】：针对当前物联网技术对功耗的严格要求,设计了一种基于分段电容的低功耗SAR ADC电路.电路通过使用分离电容阵列来降低整个CDAC所需要的单位电容数和ADC的功耗.同时采用了分离电容校正技术来降低整体CDAC的非线性和失调校正技术来降低比较器电路的失调.在0.18,mm CMOS工艺下完成了一款10-bit 10-Msample/s的电路原型设计及相应的版图设计和验证工作,带有PAD的芯片整体面积为1,2mm.芯片后仿真结果表明:该转换器在校正情况下,4.89,MHz输入信号频率下信号噪声谐波比(SFDR)为61.43,dB,比不校正提高了54%,;有效位数达到9.90,bit,比不校正提高了3.7,bit;在1.8,V电源电压下功耗仅为255.61,mW.
[Abstract]:A low power SAR ADC circuit based on piecewise capacitance is designed to meet the strict requirement of power consumption in the current Internet of things (IoT) technology. The circuit reduces the number of unit capacitors and the power consumption of ADC by using a separate capacitor array. At the same time, the separation capacitance correction technique is used to reduce the nonlinearity and offset correction of the whole CDAC to reduce the offset of the comparator circuit. A prototype design of 10-bit 10-Msample / s circuit and corresponding layout design and verification are completed in 0.18mm CMOS process. The overall area of the chip with pad is 1 mm2. The simulation results show that the signal noise to harmonic ratio (SFDR) of the converter is 61.43 dB at 4.89 MHz input frequency, which is 54 bit higher than that without correction, the effective bit is 9.90 bit, which is 3.7 bit higher than that without correction, and the power consumption is only 255.61 mW at 1.8V power supply voltage.
【作者单位】：河北工业大学电子信息工程学院;河北科技大学信息科学与工程学院;
【分类号】：TN792

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