适用于Serdes的插值型时钟数据恢复电路设计

发布时间：2018-07-06 21:13

本文选题：Serdes + 插值型　；参考：《北京交通大学》2015年硕士论文

【摘要】：随着网络和大数据的发展,人们对信息传输的需求快速增长,传统的并行接口受到越来越多的限制,高速串行接口技术逐渐成为通信中的主流方式。目前常见的串行通信协议有UART、USB和IEEE1394等。其中1394接口以其多通道、高速率等特点被广泛应用与系统总线与视频传输。1394接口由IEEE(电气与电子工程师协会)于1995年制定出传输标准,传输峰值可以达到400MB/S,同时支持100MB/S和200MB/S速率传输。2001年IEEE对1394接口重新制定规范,颁布的1394B的传输速度可以达到800MB/S,如果使用塑料光纤它的最高速度可以提高到32GB/S。本论文首先描述了串行链路的功能,阐明了Serdes中CDR(时钟数据恢复)与其他模块之间的联系。其次详细介绍了时钟数据恢复电路中抖动与数据编码的概念,对设计指标进行分析。通过对时钟数据恢复电路的结构进行对比和分析,选择相位插值型时钟数据恢复电路作为本设计的电路结构,并确定Alexander鉴相器、二阶数字环路滤波器等核心模块。然后完成各个模块的电路设计和仿真,包括采样模块、解串模块、环路滤波器、相位插值电路以及时钟选择电路。最后对整体时钟数据恢复电路进行瞬态仿真观察其眼图的抖动数据,并计算恢复时钟的锁定时间,验证是否满足1394B的设计指标。本论文设计的适用于Serdes的插值型时钟数据恢复电路,以1394B通信协议作为标准,同时支持800MHz、400MHz,100MHz三种数据频率传输,采用外部锁相环提供的4相位时钟。相位插值电路采用64位并行控制位运算,合成恢复时钟的相位精度为π／32。利用Cadence EDA工具完成原理图和版图的设计,并用Spectre完成仿真验证。通过仿真,恢复时钟的抖动和锁定时间能够满足Serdes1394B的指标,合成时钟能够对输入信号实现恢复功能。
[Abstract]:With the development of network and big data, the demand for information transmission increases rapidly, and the traditional parallel interface is restricted more and more. High speed serial interface technology has gradually become the mainstream way of communication. At present, the common serial communication protocols are UART USB and IEEE 1394. The 1394 interface is widely used with the characteristics of multi-channel, high speed and so on. The system bus and video transmission .1394 interface were formulated by IEEE (Institute of Electrical and Electronic Engineers) in 1995. The peak value of transmission can reach 400MB / S and support both 100MB / S and 200MB / S rate transmissions. In 2001, the IEEE re-standardized the 1394 interface, and the transmission speed of 1394B can reach 800MB / S, and the maximum speed of using plastic fiber can be increased to 32GB / Ss. In this paper, the function of serial link is described, and the relationship between CDR (clock data recovery) and other modules in Serdes is clarified. Secondly, the concepts of jitter and data coding in clock data recovery circuit are introduced in detail, and the design index is analyzed. By comparing and analyzing the structure of clock data recovery circuit, the phase interpolation clock data recovery circuit is selected as the circuit structure of this design, and the core modules such as Alexander phase discriminator and second-order digital loop filter are determined. Then the circuit design and simulation of each module are completed, including sampling module, de-string module, loop filter, phase interpolation circuit and clock selection circuit. Finally, the transient simulation of the whole clock data recovery circuit is carried out to observe the jitter data of the eye diagram, and the locking time of the recovery clock is calculated to verify whether it meets the design criteria of 1394B. In this paper, the interpolating clock data recovery circuit for Serdes is designed. It uses 1394B communication protocol as the standard, and supports 800MHz 400MHz 100MHz data frequency transmission. It adopts the 4-phase clock provided by the external phase-locked loop (PLL). The phase interpolation circuit uses 64 bit parallel control bit operation, and the phase precision of the synthetic recovery clock is 蟺 / 32. The schematic diagram and layout are designed with Cadence eda tool, and the simulation is done with Spectre. The simulation results show that the jitter and locking time of the recovery clock can meet the target of Serdes1394B, and the synthetic clock can recover the input signal.
【学位授予单位】：北京交通大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN402

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