脉搏和血氧饱和度传感器芯片的研究

发布时间：2018-07-09 17:05

本文选题：测量电路 + 低噪声　；参考：《天津工业大学》2017年硕士论文

【摘要】：随着半导体技术和现代传感技术的迅速发展及广泛应用,医疗检测设备也越来越微型化、集成化及智能化。因此利用半导体技术来研究一种脉搏和血氧饱和度的测量电路极为重要。本文把测量系统电路集成到芯片上,能够降低测量系统的噪声、功耗和体积,满足便携式医疗设备的要求。采用UMC 0.18μm的CMOS标准工艺设计一种脉搏和血氧饱和度传感器芯片,芯片内部电路包括两个模块:脉搏血氧测量电路和流水线模数转换器(Pipelined Analog to digital converter,Pipelined ADC)。本文首先了介绍朗伯-比尔定律(Lambert-Beer),重点分析了反射式血氧饱和度的测量原理,得到了设计芯片电路的理论模型。然后设计脉搏和血氧饱和度传感器芯片电路。脉搏血氧测量电路主要包括前置放大电路、抑制基漂电路、带通滤波电路和二级放大电路,并依次对各个子电路的性能指标进行仿真。12位Pipelined ADC的关键电路的设计,主要包括采样开关电路,高速比较器,电压基准源,乘法模数转换器(Multiplicative analog to digital converter,MDAC)单元和数字校准电路。最后分别对两个模块电路进行仿真,并且设计芯片版图。在1.8V的工作电压下,测量电路在带宽(6.5Hz～8.5kHz)范围内的系统增益为63dB,等效输入积分噪声为22.326μV,功耗为42.7mW。这样可有效减小测量系统的噪声,降低和抑制带外噪声,且能减小测量系统整体面积,适合对微弱幅度的生物医学信号的处理。Pipelined ADC的分辨率为12位,采样速率为1MHz,在 9.303kHz 的输入正弦信号下,SNR 为 68.2016dB、SNDR 为 61.7818dB、SFDR为 64.2785dB,ENOB=10.9bit。
[Abstract]:With the rapid development and wide application of semiconductor technology and modern sensing technology, medical detection equipment is becoming more and more miniaturized, integrated and intelligent. Therefore, it is very important to use semiconductor technology to study a pulse and oxygen saturation measurement circuit. In this paper, the measurement system circuit is integrated into the chip, which can reduce the noise, power consumption and volume of the measurement system, and meet the requirements of portable medical equipment. A pulse and oxygen saturation sensor chip is designed using UMC-0.18 渭 m CMOS standard process. The internal circuit of the chip consists of two modules: pulse oxygen measurement circuit and pipelined Analog to digital convertor pipelined ADC. In this paper, Lambert-Beer 's law is introduced, and the measuring principle of reflective oxygen saturation is analyzed, and the theoretical model of chip circuit design is obtained. Then the pulse and oxygen saturation sensor chip circuit is designed. Pulse oxygen measurement circuit mainly includes preamplifier circuit, suppression base drift circuit, band-pass filter circuit and two-stage amplifier circuit. The key circuits of each sub-circuit are simulated by simulation .12-bit pipelined ADC in turn. It mainly includes sampling switch circuit, high speed comparator, voltage reference source, multiplicative analog to digital convertor MDAC unit and digital calibration circuit. Finally, the two modules are simulated, and the layout of the chip is designed. Under the operating voltage of 1.8 V, the system gain is 63 dB in the bandwidth range of 6.5 Hz (8.5 kHz), the equivalent input integral noise is 22.326 渭 V, and the power consumption is 42.7 MW. In this way, the noise of the measurement system can be effectively reduced, the out-of-band noise can be reduced and the whole area of the measurement system can be reduced. The resolution of the biomedical signal processing. Pipelined ADC with weak amplitude is 12 bits. The sampling rate is 1MHz, and the SNR is 68.2016dBN SNDR under the input sinusoidal signal of 9.303kHz, the SFDR is 61.7818dBN SFDR is 64.2785dBENOBN 10.9bit.
【学位授予单位】：天津工业大学
【学位级别】：硕士
【学位授予年份】：2017
【分类号】：TN402

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